STM8L152C8T6 STMicroelectronics, STM8L152C8T6 Datasheet - Page 7

• Manufacturer Part Number: STM8L152C8T6
• Description: 8 BITS MICROCONTR
• Manufacturer: STMicroelectronics
• Series: STM8L EnergyLiter

Specifications of STM8L152C8T6

• Core Processor: STM8
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, IR, LCD, POR, PWM, WDT
• Number Of I /o: 41
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 25x12b, D/A 1x12
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

STM8L15xx8, STM8L15xR6
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
High density and medium+ density STM8L15xx device block diagram . . . . . . . . . . . . . . 13
Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
STM8L151M8 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L152M8 80-pin package pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
STM8L151R8 and STM8L151R6 64-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . 26
STM8L152R8 and STM8L152R6 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . 26
STM8L151C8 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
STM8L152C8 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Memory map
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical I
Typical I
Typical I
Typical I
Typical I
Typical I
Typical IDD(AH) vs. V
Typical IDD(Halt) vs. V
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical HSI frequency vs. V
Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Typical pull-up resistance R
Typical pull-up current I
Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Typical NRST pull-up resistance R
Typical NRST pull-up current I
Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
SPI1 timing diagram - slave mode and CPHA=1
SPI1 timing diagram - master mode
Typical application with I2C bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 104
ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Power supply and reference decoupling (V
Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 115
80-pin low profile quad flat package (14 x 14 mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LQFP64 – 10 x 10 mm, 64 pin low-profile quad flat package outline . . . . . . . . . . . . . . . . 121
Recommended footprint
DD(RUN)
DD(RUN)
DD(Wait)
DD(Wait)
DD(LPR)
DD(LPW)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
vs. V
from RAM vs. V
from Flash (HSI clock source), f
from RAM vs. V
from Flash vs. V
vs. V
DD
DD
DD
DD
pu
(1)
(LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 78
(LSI clock source), all peripherals OFF
(LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
(internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 84
vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
DD
PU
Doc ID 17943 Rev 4
pu
vs. V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
DD
DD
DD
vs. V
DD
with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
PU
(HSI clock source), f
(1)
(HSI clock source), f
DD
(HSI clock source), f
vs. V
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
REF+
DD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
(1)
not connected to V
CPU
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
= 16 MHz
CPU
CPU
CPU
= 16 MHz
=16 MHz
= 16 MHz
1)
(1)
. . . . . . . . . . . . . . . . . . . 76
DDA
. . . . . . . . . . . . . . . . . 80
1) . . . . . . . . . . . . . . . . . 73
). . . . . . . . . . . . . 115
1)
1) . . . . . . . . . . . . . . . . 73
. . . . . . . . . . . . . 76
List of figures
7/126