XR17D154IV Exar Corporation, XR17D154IV Datasheet - Page 20

• Manufacturer Part Number: XR17D154IV
• Description: Universal QUART W/ PCI Bus Interface.
• Manufacturer: Exar Corporation

Specifications of XR17D154IV

• Features: *
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
There are two internal registers that provide device identification and revision, DVID and DREV registers. The
8-bit content in the DVID register provides device identification. A return value of 0x24 from this register
indicates the device is an XR17D154 or an XR17C154. The DREV register returns an 8-bit value of 0x01 for
revision A with 0x02 equals to revision B and so forth. This information is very useful to the software driver for
identifying which device it is communicating with and to keep up with revision changes.
DVID [15:8]
Device identification for the type of UART. The upper nibble indicates it is a XR17xxxx series with lower nibble
indicating the number of channels.
Examples:
XR17D158 or XR17C158 = 0x28
XR17D154 or XR17C154 = 0x24
XR17D152 or XR17C152 = 0x22
DREV [7:0]
Revision number of the XR17D154. A 0x01 represents "revision-A" with 0x02 for rev-B and so forth.
REGB [23:16] - (default 0x00)
REGB register provides a control for simultaneous write to all 4 UARTs configuration register or individually.
This is very useful for device initialization in the power up and reset routines. Also, the register provides a
facility to interface to the non-volatile memory device such as a 93C46 EEPROM. In embedded applications,
the user can use this facility to store proprietary data.
The D154 provides 8 multi-purpose inputs/outputs [MPIO7:0] for general use. Each pin can be programmed to
be an input or output function. The input logic state can be set for normal or inverted level, and optionally set to
generate an interrupt. The outputs can be set to be normal logic 1 or 0 state, or tri-state. Their functions and
definitions are programmed through 5 registers: MPIOINT, MPIOLVL, MPIO3T, MPIOINV and MPIOSEL. If all
8 pins are set for inputs, all 8 interrupts would be OR’ed together. The Or’ed interrupt is reported in the channel
0 UART interrupt status, see Interrupt Status Register. The pins may also be programmed to be outputs and to
the tri-state condition for signal sharing.
2.2.7
2.2.9
REGB[16] (Read/Write)
REGB[19:17]
REGB[20] (Write-Only)
REGB[21] (Write-Only)
REGB[22] (Write-Only)
REGB[23] (Read-Only)
2.2.8
Device Identification and Revision
Multi-Purpose Inputs and Outputs
REGB Register
Logic 0 (default) write to each UART configuration registers individually.
Logic 1 enables simultaneous write to all 4 UARTs configuration register.
Reserved
Control the EECK, clock, output (pin 116) on the EEPROM interface.
Control the EECS, chips select, output (pin 115) to the EEPROM device.
EEDI (pin 114) data input. Write data to the EEPROM device.
EEDO (pin 113) data output. Read data from the EEPROM device.
20
xr
REV. 1.2.2