XR17D154IV Exar Corporation, XR17D154IV Datasheet - Page 28

• Manufacturer Part Number: XR17D154IV
• Description: Universal QUART W/ PCI Bus Interface.
• Manufacturer: Exar Corporation

Specifications of XR17D154IV

• Features: *
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

XR17D154
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
The transmitter section comprises of a 64 bytes of FIFO, a byte-wide Transmit Holding Register (THR) and an
8-bit Transmit Shift Register (TSR). THR receives a data byte from the host (non-FIFO mode) or a data byte
from the FIFO when the FIFO is enabled by FCR bit-0. TSR shifts out every data bit with the 16X or 8X internal
clock. A bit time is 16 or 8 clock periods. The transmitter sends the start bit followed by the number of data bits,
inserts the proper parity bit if enable, and adds the stop bit(s). The status of the THR and TSR are reported in
the Line Status Register (LSR bit-5 and bit-6).
The transmit holding register is an 8-bit register providing a data interface to the host processor. The host
writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,
parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is also the
input register to the transmit FIFO of 64 bytes when FIFO operation is enabled by FCR bit-0. A THR empty
interrupt can be generated when it is enabled in IER bit-1.
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
O
5.2
5.2.1
5.2.2
UTPUT
MCR Bit-7=1
T
ABLE
230.4k
115.2k
19.2k
38.4k
57.6k
1200
2400
4800
9600
100
600
Transmitter
Data Rate
Transmit Holding Register (THR) - Write-Only
Transmitter Operation in non-FIFO mode
10: T
YPICAL DATA RATES WITH A
O
UTPUT
MCR Bit-7=0
153.6k
230.4k
460.8k
921.6k
19.2k
38.4k
76.8k
2400
4800
9600
400
Data Rate
Clock (Decimal)
D
IVISOR FOR
2304
384
192
14.7456 MH
96
48
24
12
6
4
2
1
16x
D
28
IVISOR FOR
Clock (HEX)
Z CRYSTAL OR EXTERNAL CLOCK AT
900
180
C0
0C
60
30
18
06
04
02
01
16x
DLM P
V
ALUE
09
01
00
00
00
00
00
00
00
00
00
ROGRAM
(HEX)
DLL P
V
ALUE
C0
0C
00
80
60
30
18
06
04
02
01
ROGRAM
16X S
(HEX)
xr
AMPLING
D
E
REV. 1.2.2
ATA
RROR
0
0
0
0
0
0
0
0
0
0
0
R
ATE
(%)