XR17D154IV Exar Corporation, XR17D154IV Datasheet - Page 49

• Manufacturer Part Number: XR17D154IV
• Description: Universal QUART W/ PCI Bus Interface.
• Manufacturer: Exar Corporation

Specifications of XR17D154IV

• Features: *
• Number Of Channels: 4, QUART
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 3.3V, 5V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• Mounting Type: Surface Mount
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant

xr
REV. 1.2.2
EFR[4]: Enhanced Function Bits Enable
Enhanced function control bit. This bit enables the functions in IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 to be modified. After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the
new values. This feature prevents legacy software from altering or overwriting the enhanced functions once
set. Normally, it is recommended to leave it enabled, logic 1.
•
•
EFR[5]: Special Character Detect Enable
•
•
Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR
bits 5-7 are saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and
MCR bits 5-7 are set to a logic 0 to be compatible with the industry standard 16550 (default).
Logic 1 = Enables the enhanced functions. When this bit is set to a logic 1 all enhanced features are
enabled.
Logic 0 = Special Character Detect Disabled (default).
Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with
data in Xoff-2 register. If a match exists, the received data will be transferred to FIFO and ISR bit-4 will be set
to indicate detection of the special character. Bit-0 corresponds with the LSB bit for the receive character. If
flow control is set for comparing Xon1, Xoff1 (EFR [1:0]=’10’) then flow control and special character work
normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]=’01’) then flow control works
normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character
interrupt.
EFR
TX S/W FLOW CONTROL
C
ONT
X
X
X
0
0
1
1
0
1
0
1
BIT
-3
-3
EFR
C
ONT
X
X
X
0
1
0
1
1
0
0
1
BIT
-2
-2
T
ABLE
RX S/W FLOW CONTROL
EFR
C
ONT
19: S
X
X
X
X
0
0
1
1
1
1
1
BIT
-1
-1
OFTWARE
EFR
C
ONT
X
X
X
X
0
1
0
1
1
1
1
F
BIT
49
LOW
-0
-0
UNIVERSAL (3.3V AND 5V) PCI BUS QUAD UART
C
No transmit flow control
Transmit Xon2, Xoff2
Transmit Xon1, Xoff1
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
Receiver compares Xon2, Xoff2
Receiver compares Xon1, Xoff1
Transmit Xon2, Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1, Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
No transmit flow control
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
ONTROL
S
F
OFTWARE
UNCTIONS
F
LOW
C
ONTROL
F
UNCTIONS
XR17D154