SC16C850LIBS-G NXP Semiconductors, SC16C850LIBS-G Datasheet - Page 10

• Manufacturer Part Number: SC16C850LIBS-G
• Manufacturer: NXP Semiconductors

Specifications of SC16C850LIBS-G

• Transmitter And Receiver Fifo Counter: Yes
• Data Rate: 5Mbps
• Mounting: Surface Mount
• Pin Count: 32
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Number Of Channels: 1
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SC16C850L
Product data sheet
6.2 Extended mode (128-byte FIFO)
6.3 Internal registers
Table 4.
H = HIGH; L = LOW.
The device is in the extended mode when any of these four registers contains any value
other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.
The SC16C850L provides a set of 25 internal registers for monitoring and controlling the
functions of the UART. These registers are shown in
Table 5.
Chip Select
A2
0
0
0
0
1
1
1
1
Baud rate register set (DLL/DLM)
0
0
Second special register set (TXLVLCNT/RXLVLCNT)
0
1
Enhanced feature register set (EFR, Xon1/Xon2, Xoff1/Xoff2)
0
1
1
1
1
First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)
0
1
1
1
CS = H
CS = L
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
A1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
1
Serial port selection (Motorola interface)
Internal registers decoding
A0
0
1
0
1
0
1
0
1
0
1
1
0
0
0
1
0
1
0
0
0
1
All information provided in this document is subject to legal disclaimers.
Read mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Transmit FIFO Level Count
Receive FIFO Level Count
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Flow Control Count High
Flow Control Count Low
1.8 V single UART with 128-byte FIFOs and IrDA encoder/decoder
Function
none
UART select
Rev. 5 — 1 February 2011
[2]
[3]
Write mode
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
Extra Feature Control Register (EFCR)
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Flow Control Count High
Flow Control Count Low
Transmit Holding Register
n/a
n/a
Transmit FIFO Interrupt Level
Receive FIFO Interrupt Level
Table
[4]
5.
SC16C850L
[1]
© NXP B.V. 2011. All rights reserved.
[5]
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