ISP1507DBSUM STEricsson, ISP1507DBSUM Datasheet - Page 62

• Manufacturer Part Number: ISP1507DBSUM
• Manufacturer: STEricsson

Specifications of ISP1507DBSUM

• Lead Free Status / RoHS Status: Compliant

CD00222690
Product data sheet
Fig 21. Rise time and fall time
Fig 23. Timing of TX_ENABLE to DP and DM
1.8 V
V
V
V
V
0 V
OH
OH
OL
OL
logic
input
differential
data lines
0.9 V
t
HSR
10 %
15.1 ULPI timing
, t
FR
t
V
t
PZH
PZL
CRS
, t
LR
90 %
ULPI timing requirements are given in
mode only. All timing is measured with respect to the ISP1507 CLOCK pin. All signals are
clocked on the rising edge of CLOCK.
Fig 25. ULPI timing
CONTROL OUT
CONTROL IN
(DIR, NXT)
DATA OUT
DATA IN
CLOCK
V
V
(8-BIT)
(8-BIT)
OH
90 %
OL
(STP)
+ 0.3 V
− 0.3 V
t
HSF
t
t
0.9 V
PHZ
PLZ
10 %
, t
FF
, t
LF
t
su(DATA)
t
su(STP)
Rev. 04 — 20 May 2010
004aaa861
004aaa574
t
t
h(STP)
h(DATA)
Fig 22. Timing of TX_DAT and TX_SE0 to DP and DM
Fig 24. Timing of DP and DM to RX_RCV, RX_DP and
1.8 V
differential
data lines
V
V
0 V
logic input
OH
OL
logic output
Figure
0.8 V
2.0 V
V
V
differential
data lines
OH
OL
ULPI HS USB host and peripheral transceiver
RX_DM
0.9 V
ISP1507C; ISP1507D
25. This timing applies to synchronous
V
t
t
CRS
t
d(DIR)
d(NXT)
d(DATA)
t
PLH(drv)
,
V
t
t
PLH(se)
PLH(rcv)
CRS
0.9 V
t
t
d(DIR)
d(NXT)
© ST-ERICSSON 2010. All rights reserved.
,
t
PHL(drv)
0.9 V
t
t
V
PHL(rcv)
PHL(se)
CRS
V
004aaa575
004aaa722
004aaa573
CRS
0.9 V
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