ISP1301BS,118 NXP Semiconductors, ISP1301BS,118 Datasheet - Page 45

• Manufacturer Part Number: ISP1301BS,118
• Manufacturer: NXP Semiconductors

Specifications of ISP1301BS,118

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant

22. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. USB functional mode: transmit operation . . . .16
Table 11. Differential receiver operation settings . . . . . .16
Table 12. USB functional mode: receive operation . . . . .17
Table 13. Serial controller registers . . . . . . . . . . . . . . . . .18
Table 14. Vendor ID register: bit description . . . . . . . . . .18
Table 15. Product ID register: bit description . . . . . . . . . .18
Table 16. Version ID register: bit description . . . . . . . . . .19
Table 17. Mode Control 1 register: bit allocation . . . . . . .19
Table 18. Mode Control 1 register: bit description . . . . . .19
Table 19. Mode Control 2 register: bit allocation . . . . . . .19
Table 20. Mode Control 2 register: bit description . . . . . .20
Table 21. OTG Control register: bit allocation . . . . . . . . .20
Table 22. OTG Control register: bit description . . . . . . . .20
Table 23. OTG Status register: bit allocation . . . . . . . . . .21
Table 24. OTG Status register: bit description . . . . . . . . .21
Table 25. Interrupt Source register: bit allocation . . . . . .21
Table 26. Interrupt Source register: bit description . . . . .22
Table 27. Interrupt Latch register: bit allocation . . . . . . .22
Table 28. Interrupt Latch register: bit description . . . . . .22
Table 29. Interrupt Enable Low register: bit allocation . . .22
Table 30. Interrupt Enable Low register: bit description .23
Table 31. Interrupt Enable High register: bit allocation . .23
Table 32. Interrupt Enable High register: bit description .23
Table 33. I
Table 34. I
Table 35. I
Table 36. Transfer format description for one-byte write .27
Table 37. Transfer format description for multiple-byte
Table 38. Transfer format description for current address
Table 39. Transfer format description for single-byte
Table 40. Transfer format description for multiple-byte
Table 41. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .32
Table 42. Recommended operating conditions . . . . . . . .32
Table 43. Static characteristics: supply pins . . . . . . . . . .33
Table 44. Static characteristics: digital pins . . . . . . . . . . .33
Table 45. Static characteristics: analog I/O pins DP and
Table 46. Static characteristics: analog I/O pin ID . . . . . .34
Table 47. Static characteristics: charge pump . . . . . . . . .35
Table 48. Dynamic characteristics: reset and clock . . . . .36
Table 49. Dynamic characteristics: digital I/O pins . . . . .36
Table 50. Dynamic characteristics: analog I/O pins DP
ISP1301_5
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Recommended charge pump capacitor value .12
Device operating modes . . . . . . . . . . . . . . . . .14
USB suspend mode: I/O . . . . . . . . . . . . . . . . .14
USB functional modes: I/O values . . . . . . . . . .15
USB suspend mode: I/O values . . . . . . . . . . .15
Transparent general-purpose buffer mode . . .15
Transceiver driver operation setting . . . . . . . .16
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
2
2
2
C-bus byte transfer format . . . . . . . . . . . . . .27
C-bus device address byte 1 bit allocation . .27
C-bus device address byte 1 bit description .27
Rev. 05 — 2 September 2009
Table 51. Characteristics of I/O stages of I
Table 52. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table 53. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 44
(SDA, SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
USB OTG transceiver
© ST-ERICSSON 2009. All rights reserved.
ISP1301
2
C-bus lines
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