ISP1506BBS,551 NXP Semiconductors, ISP1506BBS,551 Datasheet - Page 14

• Manufacturer Part Number: ISP1506BBS,551
• Description: RF Transceiver USB2 ULPI DDR OTG
• Manufacturer: NXP Semiconductors

Specifications of ISP1506BBS,551

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Operating Supply Voltage (typ): Not RequiredV
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): Not RequiredV
• Operating Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOT-616
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935278349551 ISP1506BBS-S

NXP Semiconductors
ISP1506A_ISP1506B_2
Product data sheet
7.9.12.1 RESET_N
7.9.12.2 PSW_N
7.9.12 RESET_N/PSW_N
7.9.13 DIR
7.9.14 STP
This pin provides two optional functions. If neither function is used, this pin must be
connected to V
An active LOW asynchronous reset pin that resets all circuits in the ISP1506. The
ISP1506 contains an internal power-on reset circuit, and therefore using the RESET_N
pin is optional. If RESET_N is not used, it must be connected to V
For details on using RESET_N, see
PSW_N is an active LOW, open-drain output pin. This pin can be connected to an active
LOW, external V
power source. An external pull-up resistor, R
pin is open-drain, allowing ganged-mode power control for multiple USB ports. For
application details, see
To use the PSW_N pin, the link must disable the reset input by setting the
IGNORE_RESET bit in the Power Control register to logic 1. This will ensure that PSW_N
is not misinterpreted as a reset.
If the link is in host mode, it can enable the external V
DRV_VBUS_EXT bit in the OTG Control register to logic 1. The ISP1506 will drive
PSW_N to LOW to enable the external V
overcurrent condition (the V
V
ULPI direction output pin. Controls the direction of the data bus. By default, the ISP1506
holds DIR at LOW, causing the data bus to be an input. When DIR is LOW, the ISP1506
listens for data from the link. The ISP1506 pulls DIR to HIGH only when it has data to
send to the link, which is for one of two reasons:
For details on DIR usage, refer to
Rev.
ULPI stop input pin. The link must assert STP to signal the end of a USB transmit packet
or a register write operation. When DIR is asserted, the link can optionally assert STP to
abort the ISP1506, causing it to deassert DIR in the next clock cycle. A weak pull-up
resistor is incorporated into the STP pin as part of the interface protect feature. For details,
see
For details on STP usage, refer to
Rev.
BUS
•
•
To send the USB receive data, RXCMD status updates and register reads data to the
link.
To block the link from driving the data bus during power-up, reset and low-power
mode (suspend).
Section
1.1”.
1.1”.
power source by setting DRV_VBUS_EXT to logic 0.
9.3.1.
CC(I/O)
BUS
switch or charge pump enable circuit to control the external V
.
Rev. 02 — 28 August 2008
Section
BUS
16.
state in RXCMD is not 11b), it must disable the external
Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification
Ref. 3 “UTMI+ Low Pin Interface (ULPI) Specification
Section
BUS
9.3.2.
pullup
power source. If the link detects an
ISP1506A; ISP1506B
, is required when PSW_N is used. This
BUS
ULPI HS USB OTG transceiver
power source by setting the
CC(I/O)
© NXP B.V. 2008. All rights reserved.
.
BUS
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