TDA8501T/N1,112 NXP Semiconductors, TDA8501T/N1,112 Datasheet - Page 16

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TDA8501T/N1,112

Manufacturer Part Number
TDA8501T/N1,112
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of TDA8501T/N1,112

Lead Free Status / RoHS Status
Compliant
Philips Semiconductors
April 1993
PAL mode; pin 17 = 0 V
V
V
V
NTSC mode; pin 17 = 5 V and pin 4 open-circuit or ground
V
V
V
BW
t
t
Y + SYNC IN (pin 20 from delay circuit; note 2)
I
V
Y + SYNC OUT (pin 19 output Y (SVHS); note 2)
R
I
I
V
G
BW
SYMBOL
d
d
bias
sink
source
SYNC
Y
DIF
SYNC
Y
DIF
I
BL
O
PAL/NTSC encoder
sync voltage amplitude
Y voltage amplitude
difference between black and
blanking level
sync voltage amplitude
Y voltage amplitude
difference between black and
blanking level
frequency response
group delay tolerance
sync delay from pin 24 to pin 22
Y delay from pin 5 to pin 22
Chrominance cross talk
input bias current
maximum voltage amplitude
output resistance
maximum sink current
maximum source current
black level output voltage
Y
from pin 20 to pin 19
frequency response
group delay tolerance
Chrominance cross talk
SYNC gain;
PARAMETER
pin 22 with external
load of R = 10 k and
C = 10 pF
0 dB = 1330 mV
(peak-to-peak)
= 75% RED
pin 19 with external
load of R = 10 k and
C = 10 pF
0 dB = 1330 mV
(peak-to-peak)
= 75% RED
CONDITIONS
16
285
665
270
628
10
220
650
1000
10
MIN.
300
700
0
286
661
53
290
10
120
1.65
12
TYP.
Preliminary specification
315
735
300
694
20
360
1
1
20
MAX.
60
54
TDA8501
mV
mV
mV
mV
mV
mV
MHz
ns
ns
ns
dB
V
V
dB
MHz
ns
dB
A
A
A
UNIT

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