SAA7128H/V1 NXP Semiconductors, SAA7128H/V1 Datasheet - Page 44

• Manufacturer Part Number: SAA7128H/V1
• Manufacturer: NXP Semiconductors

Specifications of SAA7128H/V1

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14325
Product data sheet
Fig 20. Clock data timing
Fig 21. Functional timing
MP input data
output data
LLC1
The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode
(RCV2S).
LLC
MP(n)
RCV2
10.1 Explanation of RTCI data bits
t
SU; DAT
Refer to
•
•
•
•
•
The HPLL increment is not evaluated by the SAA7128H; SAA7129H.
The SAA7128H; SAA7129H generates the subcarrier frequency from the FSCPLL
increment if enabled (see last bullet).
The PAL bit indicates the line with inverted (R
signal.
If the reset bit is enabled (RTCE = 1; DECPH = 1; PHRES = 00), the phase of the
subcarrier is reset in each line whenever the reset bit of RTCI input is set to logic 1.
If the FISE bit is enabled (RTCE = 1; DECFIS = 1), the SAA7128H; SAA7129H takes
this bit instead of the FISE bit in subaddress 61h.
valid
MP
t
Figure
pos
HD; DAT
C
t
B
h
(0)
22:
t
HIGH
valid
not
Rev. 03 — 9 December 2004
Y(0)
t
SU; DAT
t
d
T
LLC1
not valid
t
MP
f
neg
t
HD; DAT
SAA7128H; SAA7129H
C
R
(0)
valid
not
Y) component of color difference
Y(1)
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
t
r
MP
valid
Digital video encoder
pos
C
mhb581
B
(2)
mgb699
2.6 V
1.5 V
0.6 V
2.0 V
0.8 V
2.4 V
0.6 V
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