SAA7103HV4 NXP Semiconductors, SAA7103HV4 Datasheet - Page 9

• Manufacturer Part Number: SAA7103HV4
• Manufacturer: NXP Semiconductors

Specifications of SAA7103HV4

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: PQFP
• Pin Count: 44
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
SAA7102_SAA7103_4
Product data sheet
7.1 Reset conditions
7.2 Input formatter
7.3 RGB LUT
To activate the reset a pulse at least of 2 crystal clocks duration is required.
During reset (RESET = LOW) plus an extra 32 crystal clock periods, FSVGC, VSVGC,
CBO, HSVGC and TTX_SRES are set to input mode and HSM_CSYNC and VSM are set
to 3-state. A reset also forces the I
sets it into receive condition.
After reset, the state of the I/Os and other functions is defined by the strapping pins until
an I
Table 5:
The input formatter converts all accepted PD input data formats, either RGB or Y-C
to a common internal RGB or Y-C
When double-edge clocking is used, the data is internally split into portions PPD1 and
PPD2. The clock edge assignment must be set according to the I
EDGE1 and EDGE2 for correct operation.
If Y-C
be used directly to feed the video encoder block.
The three 256 byte RAMs of this block can be addressed by three 8-bit wide signals, thus
it can be used to build any transformation, e.g. a gamma correction for RGB signals. In the
event that the indexed color data is applied, the RAMs are addressed in parallel.
The LUTs can either be loaded by an I
input through the PD port. In the latter case, 256 bytes × 3 bytes for the R, G and B LUT
are expected at the beginning of the input video line, two lines before the line that has
been defined as first active line, until the middle of the line immediately preceding the first
active line. The first 3 bytes represent the first RGB LUT data, and so on.
Pin
FSVGC
VSVGC
CBO
HSVGC
TTXRQ_XCLKO2 LOW
2
C-bus access redefines the corresponding registers; see
B
-C
R
is being applied as a 27 MB/s data stream, the output of the input formatter can
Strapping pins
Tied
LOW
HIGH
LOW
HIGH
LOW
HIGH
LOW
HIGH
HIGH
Rev. 04 — 18 January 2006
Preset
NTSC M encoding, PIXCLK fits to 640 × 480 graphics input
PAL B/G encoding, PIXCLK fits to 640 × 480 graphics input
4 : 2 : 2 Y-C
4 : 4 : 4 RGB graphics input (format 3)
input demultiplex phase: LSB = LOW
input demultiplex phase: LSB = HIGH
input demultiplex phase: MSB = LOW
input demultiplex phase: MSB = HIGH
slave (FSVGC, VSVGC and HSVGC are inputs, internal color bar is
active)
master (FSVGC, VSVGC and HSVGC are outputs)
B
2
-C
C-bus interface to abort any running bus transfer and
R
2
B
data stream.
C-bus write access or can be part of the pixel data
-C
R
graphics input (format 0)
SAA7102; SAA7103
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
Table
2
C-bus control bits
Digital video encoder
5.
B
9 of 84
-C
R
,