ADV7181CBCPZ Analog Devices Inc, ADV7181CBCPZ Datasheet - Page 10

• Manufacturer Part Number: ADV7181CBCPZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7181CBCPZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7181C
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 7. Pin Function Descriptions
Pin No.
1
2
3, 10, 24, 57
4, 11
28 to 25, 19 to 12, 8 to 5,
62 to 59
9
20
21
22
23, 58
29
30
31
32, 37, 43
Mnemonic
INT
HS/CS
DGND
DVDDIO
P0 to P19
SFL/SYNC_OUT
LLC
XTAL1
XTAL
DVDD
PWRDWN
ELPF
PVDD
AGND
NOTES
1. NC = NO CONNECT.
SFL/SYNC_OUT
DVDDIO
DVDDIO
HS/CS
DGND
DGND
P15
P14
P13
P12
P11
P10
INT
P9
P8
P7
10
11
12
13
14
15
16
1
3
9
2
4
5
6
7
8
Type
O
O
G
P
O
O
O
O
I
P
I
O
P
G
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
1
Figure 6. Pin Configuration
Description
Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
Digital Ground.
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port. Refer to Table 10 for output configuration modes.
SFL: Subcarrier Frequency Lock. This pin contains a serial output stream that
can be used to lock the subcarrier frequency when this decoder is connected
to any Analog Devices digital video encoder.
SYNC_OUT: Sliced Synchronization Output Signal Available Only in CP Mode.
Line-Locked Output Clock. This pin is for the pixel data (the range is
12.825 MHz to 110 MHz).
This pin should be connected to the 28.63636 MHz crystal or left as a no connect
if an external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the
ADV7181C. In crystal mode, the crystal must be a fundamental crystal.
Input pin for 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,
28.63636 MHz clock oscillator source to clock the ADV7181C.
Digital Core Supply Voltage (1.8 V).
A Logic 0 on this pin places the ADV7181C in a power-down mode.
The recommended external loop filter must be connected to this ELPF pin.
PLL Supply Voltage (1.8 V).
Analog Ground.
Rev. C | Page 10 of 20
ADV7181C
(Not to Scale)
TOP VIEW
48
46
40
47
45
44
43
42
41
39
38
37
36
35
34
33
A
A
A
NC
CAPC2
AGND
CML
REFOUT
AVDD
CAPY2
CAPY1
AGND
A
A
FB
NC
IN
IN
IN
IN
IN
5
4
3
2
1