ADV7181CBCPZ Analog Devices Inc, ADV7181CBCPZ Datasheet - Page 11

• Manufacturer Part Number: ADV7181CBCPZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7181CBCPZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

Pin No.
33, 45
34
35, 36, 46, 47, 48, 49
38, 39
40
41
42
44
50
51
52
53
54
55
56
63
64
1
G = ground, I = input, O = output, I/O = input/output, and P = power.
Mnemonic
NC
FB
A
CAPY1, CAPY2
AVDD
REFOUT
CML
CAPC2
SOG/SOY
RESET
ALSB
SDATA
SCLK
VS_IN
HS_IN/CS_IN
FIELD/DE
VS
IN
1 to A
IN
6
Type
I
I
I
P
O
O
I
I
I
I
I/O
I
I
I
O
O
1
Description
No Connect. These pins are not connected internally.
Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
Analog Video Input Channels.
ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
Analog Supply Voltage (3.3 V).
Internal Voltage Reference Output. See Figure 9 for a recommended capacitor
network for this pin.
Common-Mode Level Pin (CML) for the Internal ADCs. See Figure 9 for a
recommended capacitor network for this pin.
ADC Capacitor Network. See Figure 9 for a recommended capacitor network
for this pin.
Sync on Green/Sync on Luma Input. Used in embedded synchronization mode.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms
is required to reset the ADV7181C circuitry.
This pin selects the I
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
I
I
VS Input Signal. Used in CP mode for 5-wire timing mode.
This pin can be configured in CP mode to be either a digital HS input signal or
a digital CS input signal used to extract timing in a 5-wire or 4-wire RGB mode.
Field Synchronization Output Signal (All Interlaced Video Modes). This pin
also can be enabled as a data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
Vertical Synchronization Output Signal (SDP and CP Modes).
2
2
Rev. C | Page 11 of 20
C Port Serial Data Input/Output Pin.
C Port Serial Clock Input. Maximum clock rate of 400 kHz.
2
C address for the ADV7181C control and VBI readback
ADV7181C