ADV7181CBCPZ Analog Devices Inc, ADV7181CBCPZ Datasheet - Page 6

• Manufacturer Part Number: ADV7181CBCPZ
• Manufacturer: Analog Devices Inc

Specifications of ADV7181CBCPZ

• Adc/dac Resolution: 10b
• Screening Level: Industrial
• Package Type: LFCSP EP
• Pin Count: 64
• Lead Free Status / RoHS Status: Compliant

ADV7181C
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. T
unless otherwise noted.
Table 3.
Parameter
SYSTEM CLOCK AND CRYSTAL
I
RESET FEATURE
CLOCK OUTPUTS
DATA AND CONTROL OUTPUTS
1
2
3
4
5
6
2
The minimum/maximum specifications are guaranteed over this range.
Guaranteed by characterization.
TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
DDR timing specifications dependent on LLC output pixel clock; TLLC/4 = 9.25 ns at LLC = 27 MHz.
C PORT
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
Reset Pulse Width
LLC Mark Space Ratio
Data Output Transition Time SDR (SDP)
Data Output Transition Time SDR (SDP)
Data Output Transition Time SDR (CP)
Data Output Transition Time SDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
Data Output Transition Time DDR (CP)
3
1, 2
5
5
5, 6
5, 6
5, 6
5, 6
4
4
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
1
2
3
4
5
6
7
8
9
11
12
13
14
15
16
17
18
:t
10
Test Conditions
Negative clock edge
to start of valid data
End of valid data to
negative clock edge
End of valid data to
negative clock edge
Negative clock edge
to start of valid data
Positive clock edge
to end of valid data
Positive clock edge
to start of valid data
Negative clock edge
to end of valid data
Negative clock edge
to start of valid data
Rev. C | Page 6 of 20
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
5
45:55
−4 + TLLC/4
0.25 + TLLC/4
−2.95 + TLLC/4
−0.5 + TLLC/4
Typ
28.63636
0.6
MIN
to T
MAX
Max
±50
110
110
400
300
300
55:45
3.6
2.4
2.8
0.1
= −40°C to +85°C,
Unit
MHz
ppm
kHz
MHz
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty cycle
ns
ns
ns
ns
ns
ns
ns
ns