L-USS820D-DB LSI, L-USS820D-DB Datasheet - Page 35

• Manufacturer Part Number: L-USS820D-DB
• Manufacturer: LSI

Specifications of L-USS820D-DB

• Operating Temperature (min): -20C
• Operating Temperature Classification: Commercial
• Operating Temperature (max): 85C
• Rad Hardened: No
• Lead Free Status / RoHS Status: Compliant

Data Sheet, Rev. 7
September 2004
Agere Systems Inc.
Register Interface
Table 30. System Control Register (SCR)—Address: 11H; Default: 0000 0000B
This register controls the FIFO mode, IRQ mask, and IRQ mode selection.
Bit
7
6
5
4
3
2
1
0
IRQPOL
Bit 7
IE_RESET Enable RESET Interrupt. When set, the RESET interrupt is enabled.
IE_SUSP
SRESET
IRQPOL
Symbol
RWUPE
IRQLVL
T_IRQ
—
RWUPE
IRQ Polarity. Determines the polarity of the IRQN output. When asserted, the IRQN output is
active-high (default is active-low). Firmware must be careful to ensure that setting this bit does
not cause a false interrupt to be detected and processed.
Enable Remote Wake-Up Feature. When set, remote wake-up is enabled.
Enable SUSPEND Interrupt. When set, the SUSPEND interrupt is enabled.
Software RESET. Setting this bit to 1 in software places the USS-820D in the RESET state.
This is equivalent to asserting the hardware RESET pin, except that this feature is not available
if the device is suspended. Setting this bit back to 0 leaves the USS-820D in an unconfigured
state that follows a hardware RESET.
If MCSR.FEAT = 1, SSR.SUPPO = 0 and MCSR.SUSPLOE = 0:
Interrupt Mode. Level mode interrupt is selected when this bit is cleared. Pulse mode interrupt
is selected when this bit is set. In pulse mode, IRQ signal is driven (high or low, depending on
the IRQPOL setting) by USS-820D for two t
Global Interrupt Enable. When this bit is set, it enables hardware interrupt to be generated on
IRQ pin when any of TX/RX bits, ASOF bit, RESET bit, or SUSPEND bit is set.
Reserved. Write 0 to this bit. Reads always return 0.
Bit 6
wake up the device as if a remote wake-up had been performed, with the following excep-
tions: 1) RESUME signaling is not transmitted to the host, 2) The feature is enabled regard-
less of the SCR.RWUPE setting, and 3) The MCSR.RWUPR register bit does not set. The
actual setting of the SCR.SRESET register bit does not occur until the device is resumed
and internal clocks are enabled, but the wake-up is initiated immediately. Once the wake-up
is complete, the SRESET bit sets, and the behavior is the same as if SRESET had been set
while the device was awake. Since the host will still expect the device to be suspended, this
feature should not be used with bus-powered devices, since the device will exceed the
SUSPEND power requirement.
This bit may also be set to 1 while the device is suspended. The effect of this write is to
(continued)
IE_SUSP
Bit 5
IE_RESET
Bit 4
R/W
Function/Description
SRESET
Bit 3
CLK
periods.
IRQLVL
Bit 2
USB Device Controller
T_IRQ
Bit 1
USS-820D
Bit 0
—
—
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