TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 25

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

6.3
e2v semiconductors SAS 2009
Programmable DSP Clock
Figure 6-1.
Notes:
Figure 6-2.
For correct synchronization of the MUXDAC with the DSP/FPGA/ASIC circuit intended to send the digital
data to the MUXDAC, a DSP output clock is provided by the MUXDAC.
To finely synchronize the two devices (MUXDAC and DSP/FPGA/ASIC), a programmable delay can be
applied to the DSP clock. This delay is controlled via the CS_0, CS_1, CS_2 and CS_3 bits and has a
range of 3.1 ns in 200 ps discrete steps.
Please also refer to
The [CS_0;3] bits are TTL signals (1 = TTL high, 10 kΩ or left open, 0 = TTL low or ground via 10Ω or
less) but can also be implemented as shown in
CW_IN_T/CW_IN_F
(single
(single
(differential)
1. A counter can be used to determine when the clock can be enabled after power-up.
2. If the clock starts as illustrated below, there is no guarantee that the DACs will start synchronously (they
CW_IN_T
CW_IN_F
Case 2:
Case 3:
Case 1:
may start on different edges of the clock). It is essential that the clock starts with clean transitions.
ended)
ended)
VEED / VEEA
Synchronization of Multiple TS86101G2B Devices
Clock Transition at Power-up
-
-
“Functional Description” on page
0V
100%
Power up
DAC in RESET state
Clock held high or low
Clock held high
Figure 6-3 on page
Clock held low
End of reset
20.
50% of
VEEA/VEED
26.
100 ps min
100 ps min
100 ps min
90% of VEEA/VEED
-5V
TS86101G2B
0992D–BDC–04/09
25