TS86101G2BCGL E2V, TS86101G2BCGL Datasheet - Page 5

• Manufacturer Part Number: TS86101G2BCGL
• Manufacturer: E2V

Specifications of TS86101G2BCGL

• Lead Free Status / RoHS Status: Not Compliant

Table 2-3.
e2v semiconductors SAS 2009
Parameter
DSP Clock Output (DSP_CK_T, DSP_CK_F)
Logic compatibility
Digital output voltages (true or false signals):
- Logic 0 voltage
- Logic 1 voltage (only depends on V
- Swing (on each single-ended output)
- Common mode voltage
Analog Outputs
Differential full-scale output voltage (100Ω differentially terminated)
Full-scale output power (differential output)
Full-scale power at 1/
Single-ended full-scale output voltage (50Ω terminated)
Full-scale output power (single-ended output)
Single ended mid-scale output voltage (50Ω terminated)
Output capacitance (from each single-ended output to ground)
Output VSWR (50Ω // 2 pF load on each single-ended output):
- From DC to 600 MHz
- From 600 MHz to 1.5 GHz
Deviation from theoretical Sinx/x
(50Ω // 2 pF load on each single ended output at Fs = 1.2 Gsps)
Fout up to 600 MHz
AC Performance
Single tone
Spurious free dynamic range
Fs = 600 Msps; Fout = 12.5 MHz (–6 dBFS)
Fs = 600 Msps; Fout = 287.5 MHz (–6 dBFS)
Fs = 1.2 Gsps; Fout = 25 MHz (–6 dBFS)
Fs = 1.2 Gsps; Fout = 575 MHz (–6 dBFS)
Electrical Operating Characteristics: V
(Continued)
2
balun output 50Ω terminated)
(1)
:
CCD
)
CCD
= 5V, V
Symbol
(OUT_T,
OUT_F)
OUT_T
OUT_F
VSWR
P
P
P
SFDR
C
Vpp
V
V
CM
OUT
OUT
OUT
or
OUT
OH
OL
D
B
S
EEA
and V
Level
Test
4
1
4
4
5
4
4
4
4
1
4
4
EED
PECL/LVDS (providing AC coupling capacitors and pull-
V
V
down resistors to change the common mode voltage)
= –5V, LVDS Input Level, T
CCD
CCD
Min
0.15
61
67
57
67
58
64
53
63
–0.38
–0.22
V
V
CCD
CCD
–600
Typ
0.19
4.75
–1.5
65
71
62
72
62
68
58
68
2
7
7
1
4
1
–0.35
–0.16
TS86101G2B
0992D–BDC–04/09
V
V
CCD
CCD
1.25:1
2.75:1
Max
0.22
–2.0
J
= 85°C
–0.30
–0.13
dBFS
dBFS
dBFS
dBFS
Unit
dBm
dBm
dBm
Vpp
Vpp
Vpp
dBc
dBc
dBc
dBc
mV
pF
dB
V
V
V
5