RD38F2240WWZDQ1 Micron Technology Inc, RD38F2240WWZDQ1 Datasheet - Page 37

• Manufacturer Part Number: RD38F2240WWZDQ1
• Manufacturer: Micron Technology Inc

Specifications of RD38F2240WWZDQ1

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

128-Mbit W18 Family with Synchronous PSRAM
9.0
Note:
9.1
9.1.1
9.1.2
Figure 25: PSRAM Timing Waveform for Power-Up Sequence
9.2
November 2007
Order Number: 311760-10
P-CS#
P-VCC/
VCCQ
Device Operations
Refer to the Numonyx™ Wireless Flash Memory Datasheet for detailed flash die
information.
PSRAM device operations are described in the sections that follow.
Device Power-Up/Down
Flash Power and Reset Specifications
Refer to the Intel
I/O doc #290701 and ADMux I/O doc #313272) for detailed information.
PSRAM Power-Up Sequence and Initialization
The power-on and initialization sequence ensures that the device is properly
preconditioned to operate as expected. Like conventional DRAMs, the PSRAM must be
powered up and initialized in a predefined manner. VCC and VCCQ must be applied at
the same time to the specified voltage while the input signals are held in a deselected
state (CS# = High).
After power on, an initial pause of 150 µs is required prior to the control register access
or normal operation. Failure to follow these steps may lead to unpredictable behavior.
The default operation mode after power up is the asynchronous (SRAM) mode.
PSRAM Operating Modes
The PSRAM can be used in three different operating modes:
• SRAM (full asynchronous) mode: In this mode the PSRAM applies the standard
• Fully Synchronous mode: In this mode, both read and write accesses are
• NOR-Flash mode: In this mode, reads are performed synchronously with respect to
asynchronous SRAM protocol to perform read and write accesses. In additions,
reads may be performed in page mode if the page mode is properly enabled by
programming the RCR. In this mode the clock must always remain static low.
performed synchronously with respect to the clock. Synchronous operations are
defined by the states of the control signals CE#, ADV#, OE#, WE# and UB#, LB#
at the positive (default) edge of the clock.
the clock and writes are performed asynchronously. The asynchronous write
operation requires that the clock remain static low during the entire write.
Synchronous read operations are defined by the states of the control signals CE#,
ADV#, OE#, WE# and UB#, LB# at the positive (default) edge of the clock.
P-Vcc MIN
®
Wireless Flash Memory (W18) Datasheet (order number: Non-Mux
Device Initialization
tPU >= 150
μs
§
Device ready for normal operation
Datasheet
37