MT46H64M16LFCK-6:A Micron Technology Inc, MT46H64M16LFCK-6:A Datasheet - Page 52
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MT46H64M16LFCK-6:A
Manufacturer Part Number
MT46H64M16LFCK-6:A
Description
Manufacturer
Micron Technology Inc
Type
DDR SDRAMr
Datasheet
1.MT46H64M16LFCK-6A.pdf
(96 pages)
Specifications of MT46H64M16LFCK-6:A
Organization
64Mx16
Density
1Gb
Address Bus
14b
Access Time (max)
6.5/5.5ns
Maximum Clock Rate
166MHz
Operating Supply Voltage (typ)
1.8V
Package Type
VFBGA
Operating Temp Range
0C to 70C
Operating Supply Voltage (max)
1.95V
Operating Supply Voltage (min)
1.7V
Supply Current
115mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT46H64M16LFCK-6:A
Manufacturer:
MICRON
Quantity:
11 200
Part Number:
MT46H64M16LFCK-6:A
Manufacturer:
MICRON
Quantity:
20 000
Company:
Part Number:
MT46H64M16LFCK-6:A TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Extended Mode Register
Figure 19: Extended Mode Register
Temperature-Compensated Self Refresh
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
En + 2
0
0
1
1
En + 1
0
1
0
1
En
0
–
...
0
–
Mode Register Definition
Standard mode register
Status register
Extended mode register
Reserved
Notes:
E10
0
–
E9
The EMR controls additional functions beyond those set by the mode registers. These
additional functions include drive strength, TCSR, and PASR.
The EMR is programmed via the LOAD MODE REGISTER command with BA0 = 0 and
BA1 = 1. Information in the EMR will be retained until it is programmed again, the de-
vice goes into deep power-down mode, or the device loses power.
0
This device includes a temperature sensor that is implemented for automatic control of
the self refresh oscillator. Programming the temperature-compensated self refresh
(TCSR) bits will have no effect on the device. The self refresh oscillator will continue to
refresh at the optimal factory-programmed rate for the device temperature.
–
n + 2
1
1. On-die temperature sensor is used in place of TCSR. Setting these bits will have no effect.
2. The integer n is equal to the most significant address bit.
BA1
E8
0
–
n + 1
0
BA0
E7–E0
Valid
–
An
n
...
Operation
Normal AR operation
All other states reserved
...
10
A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
E7
9
0
0
0
0
1
1
1
1
E6
8
0
0
1
1
0
0
1
1
52
E5
7
0
1
0
1
0
1
0
1
DS
6
1Gb: x16, x32 Mobile LPDDR SDRAM
5
Micron Technology, Inc. reserves the right to change products or specifications without notice.
E2
0
0
0
0
1
1
1
1
TCSR
4
E1
0
0
1
1
0
0
1
1
1
3
E0
0
1
0
1
0
1
0
1
2
Partial-Array Self Refresh Coverage
Full array
1/2 array
1/4 array
Reserved
Reserved
1/8 array
1/16 array
Reserved
PASR
Extended Mode Register
1
0
© 2007 Micron Technology, Inc. All rights reserved.
Address bus
Extended mode
register (Ex)