MT47H128M8HQ-3:G Micron Technology Inc, MT47H128M8HQ-3:G Datasheet - Page 47
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MT47H128M8HQ-3:G
Manufacturer Part Number
MT47H128M8HQ-3:G
Description
Manufacturer
Micron Technology Inc
Type
DDR2 SDRAMr
Datasheet
1.MT47H128M8HQ-3G.pdf
(134 pages)
Specifications of MT47H128M8HQ-3:G
Organization
128Mx8
Density
1Gb
Address Bus
17b
Access Time (max)
450ps
Maximum Clock Rate
667MHz
Operating Supply Voltage (typ)
1.8V
Package Type
FBGA
Operating Temp Range
0C to 85C
Operating Supply Voltage (max)
1.9V
Operating Supply Voltage (min)
1.7V
Supply Current
135mA
Pin Count
60
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MT47H128M8HQ-3:G
Manufacturer:
MICRON
Quantity:
5 520
Company:
Part Number:
MT47H128M8HQ-3:G TR
Manufacturer:
Micron Technology Inc
Quantity:
10 000
Table 17: Differential Input Logic Levels
All voltages referenced to V
Figure 13: Differential Input Signal Levels
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. V 6/10 EN
Parameter
DC input signal voltage
DC differential input voltage
AC differential input voltage
AC differential cross-point voltage
Input midpoint voltage
Notes:
Notes:
SS
V
DDQ
1.075V
0.725V
1. V
2. V
3. V
4. The typical value of V
5. V
6. V
–0.30V
1. TR and CP may not be more positive than V
2. TR represents the CK, DQS, RDQS, LDQS, and UDQS signals; CP represents CK#, DQS#,
3. This provides a minimum of 850mV to a maximum of 950mV and is expected to be
4. TR and CP must cross in this region.
5. TR and CP must meet at least V
6. TR and CP must have a minimum 500mV peak-to-peak swing.
= 1.8V
2.1V
0.9V
CP 2
TR 2
CK#, DQS, DQS#, LDQS, LDQS#, UDQS, UDQS#, and RDQS, RDQS#.
V
input (such as CK#, DQS#, LDQS#, UDQS#) level. The minimum value is equal to V
V
V
mentary input (such as CK#, DQS#, LDQS#, UDQS#, RDQS#) level. The minimum value is
equal to V
and V
differential input signals must cross, as shown in Figure 13.
the true input (CK, DQS) level and V
is expected to be approximately 0.5 × V
RDQS#, LDQS#, and UDQS# signals.
V
IN(DC)
ID(DC)
TR
IL(DC)
ID(AC)
TR
MP(DC)
DDQ
DDQ
is the true input (such as CK, DQS, LDQS, UDQS) level and V
is the true input (such as CK, DQS, LDQS, UDQS, RDQS) level and V
Input Electrical Characteristics and Operating Conditions
/2.
+ 300mV allowed provided 1.9V is not exceeded.
IX(AC)
. Differential input signal levels are shown in Figure 13.
X
specifies the allowable DC execution of each input of differential pair such as CK,
specifies the input differential voltage |V
specifies the input differential voltage |V
specifies the input differential common mode voltage (V
IH(AC)
is expected to track variations in V
Symbol
V
V
V
V
V
MP(DC)
IN(DC)
ID(DC)
ID(AC)
IX(AC)
- V
IL(AC)
IX(AC)
, as shown in Table 16 (page 46).
47
0.50 × V
is expected to be about 0.5 × V
X
ID(DC)min
–300
Min
250
500
850
DDQ
CP
Micron Technology, Inc. reserves the right to change products or specifications without notice.
- 175
is the complementary input (CK#, DQS#). V
DDQ
when static and is centered around V
.
DDQ
1Gb: x4, x8, x16 DDR2 SDRAM
DDQ
+ 0.3V or more negative than V
TR
TR
V
V
V
. V
IN(DC)max
MP(DC)
IN(DC)min
0.50 × V
- V
- V
IX(AC)
3
CP
CP
1
1
V
| required for switching, where
| required for switching, where
IX(AC)
V
V
V
Max
950
indicates the voltage at which
4
DDQ
DDQ
DDQ
DDQ
DDQ
V
ID(DC)
© 2004 Micron Technology, Inc. All rights reserved.
+ 175
of the transmitting device
5
V
CP
ID(AC)
TR
6
is the complementary
+ V
CP
CP
Units
)/2 where V
is the comple-
mV
mV
mV
mV
mV
MP(DC)
SS
Notes
IH(DC)
- 0.3V.
MP(DC)
1, 6
2, 6
3, 6
.
4
5
TR
is
-