MT46H64M16LFCK-75:A Micron Technology Inc, MT46H64M16LFCK-75:A Datasheet - Page 26

• Manufacturer Part Number: MT46H64M16LFCK-75:A
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46H64M16LFCK-75:A

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 14b
• Access Time (max): 6.5/6ns
• Maximum Clock Rate: 133MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: VFBGA
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 1.95V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 105mA
• Pin Count: 60
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Table 10: Electrical Characteristics and Recommended AC Operating Conditions (Continued)
Notes 1–9 apply to all the parameters in this table; V
PDF: 09005aef82ce3074
1gb_ddr_mobile_sdram_t48m.pdf - Rev. L 04/10 EN
Parameter
DQS write preamble setup time
DQS write postamble
Write recovery time
Internal WRITE-to-READ
command delay
Exit power-down mode to first
valid command
Exit self refresh to first valid
command
Notes:
10. Clock frequency change is only permitted during clock stop, power-down, or self refresh
11. In cases where the device is in self refresh mode for
1. All voltages referenced to V
2. All parameters assume proper device initialization.
3. Tests for AC timing and electrical AC and DC characteristics may be conducted at nomi-
4. The circuit shown below represents the timing reference load used in defining the rele-
5. The CK/CK# input reference voltage level (for timing referenced to CK/CK#) is the point
6. A CK and CK# input slew rate ≥1 V/ns (2 V/ns if measured differentially) is assumed for
7. All AC timings assume an input slew rate of 1 V/ns.
8. CAS latency definition: with CL = 2, the first data element is valid at (
9. Timing tests may use a V
nal supply voltage levels, but the related specifications and device operation are guaran-
teed for the full voltage ranges specified.
vant timing parameters of the device. It is not intended to be either a precise representa-
tion of the typical system environment or a depiction of the actual load presented by a
production tester. System designers will use IBIS or other simulation tools to correlate
the timing reference load to system environment. Specifications are correlated to produc-
tion test conditions (generally a coaxial transmission line terminated at the tester elec-
tronics). For the half-strength driver with a nominal 10pF load, parameters
are expected to be in the same range. However, these parameters are not subject to
production test but are estimated by design/characterization. Use of IBIS or other simula-
tion tools for system design validation is suggested.
at which CK and CK# cross; the input reference voltage level for signals other than CK/
CK# is V
all parameters.
clock at which the READ command was registered; for CL = 3, the first data element is
valid at (2 ×
timing is still referenced to V
ing reference voltage level is V
mode.
of the clock and ends when CKE transitions HIGH.
Symbol
t
WPRES
t
I/O
t
WPST
t
t
WTR
t
XSR
WR
XP
Full drive strength
DDQ
50
Min
132
/2.
0.4
15
t
0
2
2
CK +
Electrical Specifications – AC Operating Conditions
-5
DD
t
Max
AC) after the first clock at which the READ command was registered.
0.6
/V
–
–
–
–
–
20pF
DDQ
IL
-to-V
26
= 1.70–1.95V
Min
132
0.4
15
SS
0
2
2
DDQ
.
I/O
IH
DDQ
-54
/2 or to the crossing point for CK/CK#. The output tim-
swing of up to 1.5V in the test environment, but input
Half drive strength
Max
/2.
1Gb: x16, x32 Mobile LPDDR SDRAM
0.6
–
–
–
–
–
Micron Technology, Inc. reserves the right to change products or specifications without notice.
50
Min
132
0.4
15
0
1
2
-6
Max
0.6
10pF
–
–
–
–
–
t
CKE,
t
Min
132
CKE starts at the rising edge
0.4
15
0
1
2
© 2007 Micron Technology, Inc. All rights reserved.
-75
Max
0.6
–
–
–
–
–
t
CK +
Unit
t
t
t
ns
CK
ns
CK
CK
ns
t
t
AC) after the
AC and
Notes
24, 25
26
27
28
t
QH