MT48LC16M16A2TG-75 IT:DTR Micron Technology Inc, MT48LC16M16A2TG-75 IT:DTR Datasheet
![no-image](/images/manufacturer_photos/0/4/441/micron_technology_inc_sml.jpg)
MT48LC16M16A2TG-75 IT:DTR
Specifications of MT48LC16M16A2TG-75 IT:DTR
Related parts for MT48LC16M16A2TG-75 IT:DTR
MT48LC16M16A2TG-75 IT:DTR Summary of contents
Page 1
... SDRAM t WR CLK 2 2 (400 mil) 2 (400 mil) 1. See Micron technical note TN-48-05 on Micron's Web site. 2. Off-center parting line. 3. Contact Micron for availability. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 2
... MT48LC64M4A2BB MT48LC32M8A2TG MT48LC32M8A2P 1 MT48LC32M8A2FB 1 MT48LC32M8A2BB MT48LC16M16A2TG MT48LC16M16A2P MT48LC16M16A2FG MT48LC16M16A2BG 1. Actual FBGA part marking is shown in Package Dimensions (page 15). Note: FBGA Part Marking Decoder Due to space limitations, FBGA-packaged components have an abbreviated part marking that is different from the part number. Micron’s FBGA part marking decoder is available at www.micron.com/decoder. ...
Page 3
... PRECHARGE Operation .................................................................................................................................. 68 Auto Precharge ........................................................................................................................................... 68 AUTO REFRESH Operation ............................................................................................................................. 80 SELF REFRESH Operation .............................................................................................................................. 82 Power-Down .................................................................................................................................................. 84 Clock Suspend ............................................................................................................................................... 85 PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, x8, x16 SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 4
... Table 18: Truth Table – Current State Bank n, Command to Bank m ................................................................ 39 Table 19: Truth Table – CKE .......................................................................................................................... 41 Table 20: Burst Definition Table .................................................................................................................... 48 PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, x8, x16 SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 5
... Figure 47: WRITE With Auto Precharge .......................................................................................................... 76 Figure 48: WRITE Without Auto Precharge ..................................................................................................... 77 Figure 49: Single WRITE With Auto Precharge ................................................................................................ 78 Figure 50: Single WRITE Without Auto Precharge ........................................................................................... 79 PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, x8, x16 SDRAM t t RCD (MIN)/ CK < 3 ......................................................... 50 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 6
... Figure 54: Clock Suspend During WRITE Burst ............................................................................................... 85 Figure 55: Clock Suspend During READ Burst ................................................................................................ 86 Figure 56: Clock Suspend Mode ..................................................................................................................... 87 PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, x8, x16 SDRAM 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 7
... A[12:0] select the row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The SDRAM provides for programmable read or write burst lengths (BL locations, or the full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence ...
Page 8
... DECODER SENSE AMPLIFIERS 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN- 11 ADDRESS COUNTER/ LATCH 8 256Mb: x4, x8, x16 SDRAM Functional Block Diagrams BANK3 BANK2 BANK1 BANK0 MEMORY 1 ARRAY DATA OUTPUT 4 REGISTER 8192 I/O GATING DATA INPUT ...
Page 9
... DECODER SENSE AMPLIFIERS 2 DQM MASK LOGIC BANK READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 2 COLUMN- 10 ADDRESS COUNTER/ LATCH 9 256Mb: x4, x8, x16 SDRAM Functional Block Diagrams BANK3 BANK2 BANK1 BANK0 MEMORY 1 ARRAY DATA OUTPUT 8 REGISTER 8192 I/O GATING DATA INPUT ...
Page 10
... READ DATA LATCH CONTROL WRITE DRIVERS LOGIC 512 (x16) COLUMN DECODER COLUMN- 9 ADDRESS COUNTER/ LATCH 10 256Mb: x4, x8, x16 SDRAM Functional Block Diagrams BANK3 BANK2 2 DATA OUTPUT 16 REGISTER DATA INPUT 16 REGISTER Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 11
... DQ5 10 DQ6 SSQ NC DQ7 DQML CAS RAS CS BA0 20 - BA1 A10 - pin function is the same as the x16 pin function. 11 256Mb: x4, x8, x16 SDRAM x16 DQ15 DQ7 SSQ DQ14 DQ13 DQ6 DQ3 DDQ DQ12 DQ11 DQ5 SSQ DQ10 DQ9 DQ4 DQ2 DDQ ...
Page 12
... V DQ0 SSQ DDQ F V DQ1 SSQ WE# CAS# K RAS CS# M BA1 BA0 N A0 A10 256Mb: x4, x8, x16 SDRAM 32 Meg x 8 SDRAM 8mm x 16mm DQ7 SSQ V DQ6 DDQ DQ5 SSQ V DQ4 DDQ DQM NC CK A12 CKE A11 Depopulated Balls Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 13
... DDQ DQ11 V SSQ DQ9 V DDQ DQ8 CLK CKE A12 A11 Depopulated Balls illustrate that rows 4, 5, and 6 exist, but contain no solder balls. 13 256Mb: x4, x8, x16 SDRAM DQ0 V DDQ DD V DQ2 DQ1 SSQ V DQ4 DQ3 DDQ V DQ6 DQ5 SSQ LDQM DQ7 V DD ...
Page 14
... Type Description CLK Input Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CLK. CLK also increments the internal burst counter and controls the output registers. CKE Input Clock enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. Deactivating the clock provides precharge power-down and SELF REFRESH operation (all banks idle), active pow- er-down (row active in any bank), or CLOCK SUSPEND operation (burst/access in progress) ...
Page 15
... Rev. N 1/10 EN 22.22 ±.08 2X 0.71 2X 0.10 2.80 0.10 SEE DETAIL A 0.25mm per side. 15 256Mb: x4, x8, x16 SDRAM Package Dimensions 0.10 1.2 MAX 0.375 ±0.075 TYP 0.80 TYP (FOR REFERENCE ONLY) PLATED LEAD FINISH: 90% Sn, 10 100%Sn PLASTIC PACKAGE MATERIAL: EPOXY NOVOLAC PACKAGE WIDTH AND LENGTH DO NOT INCLUDE MOLD PROTRUSION ...
Page 16
... BALL #1 ID 0.80 TYP BALL A1 0.80 TYP C L 11.20 2.80 4.00 ±0.05 16 256Mb: x4, x8, x16 SDRAM Package Dimensions SOLDER BALL MATERIAL: 62% Sn, 36% Pb 96.5% Sn. 3% Ag, 0.5% Cu SUBSTRATE: PLASTIC LAMINATE ENCAPSULATION MATERIAL: EPOXY NOVOLAC BALL #1 ID 1.20 MAX Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 17
... TYP C L 14.00 ±0.10 7.00 ±0. 4.00 ±0.05 8.00 ±0.10 17 256Mb: x4, x8, x16 SDRAM Package Dimensions 1.00 MAX MOLD COMPOUND: EPOXY NOVOLAC SUBSTRATE MATERIAL: PLASTIC LAMINATE SOLDER BALL MATERIAL: 62% Sn, 36% Pb 96.5% Sn, 3%Ag, 0.5% Cu SOLDER MASK DEFINED BALL PADS: Ø 0.40 Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
Page 18
... Temperature and Thermal Impedance It is imperative that the SDRAM device’s temperature specifications, shown in Table 5 (page 18), be maintained to ensure the junction temperature is in the proper operat- ing range to meet data sheet specifications. An important step in maintaining the proper junction temperature is using the device’s thermal impedances correctly. The thermal impedances are listed in Table 6 (page 19) for the applicable die revision and packages being made available ...
Page 19
... JA (°C/W) Θ JA (°C/W) Airflow = Airflow = 0m/s 1m 64.9 51.5 67 40.9 Engineering to confirm thermal impedance values. as typical. 22.22mm 11.11mm 19 256Mb: x4, x8, x16 SDRAM Θ JA (°C/W) Airflow = Θ JB (°C/W) Θ JC (°C/W) 2m/s 63.8 57.6 45.3 47.3 44.5 39.1 50.8 44.8 31.4 41.6 38.1 31.4 51 ...
Page 20
... Rev. N 1/10 EN Temperature and Thermal Impedance 8.00mm 4.00mm Test point 8.00mm 4.00mm Test point 20 256Mb: x4, x8, x16 SDRAM 14.00mm 7.00mm 16.00mm 8.00mm Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 21
... IH,max DDQ be greater than one-third of the cycle rate. V width ≤3ns. 21 256Mb: x4, x8, x16 SDRAM Electrical Specifications Symbol Min Max V /V –1 +4.6 DD DDQ V – ...
Page 22
... PC100 specifies a maximum of 4pF. 3. PC100 specifies a maximum of 5pF. 4. PC100 specifies a maximum of 6.5pF. 5. PC133 specifies a minimum of 2.5pF. 6. PC133 specifies a minimum of 2.5pF. 7. PC133 specifies a minimum of 3.0pF. PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev DDQ biased at 1.4V. 22 256Mb: x4, x8, x16 SDRAM Electrical Specifications Symbol Min Max C 2.5 3 2.5 3.8 L2 ...
Page 23
... The two AUTO REFRESH com- SS SSQ mand wake-ups should be repeated any time the test conditions have V DD reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is 23 256Mb: x4, x8, x16 SDRAM DD Symbol -6A I 135 DD1 I ...
Page 24
... DD quency alteration for the test condition. is actually a nominal value and does not result in a fail value. 24 256Mb: x4, x8, x16 SDRAM DD and no longer from the 1.5V midpoint. CLK should t RFC (MIN) else CKE is LOW. The I Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
Page 25
... OH t OHn t RAS RCD t REF t REF AT t RFC RRD XSR 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 SDRAM -6A Min Max Unit Notes – 5 – 0.8 ns – 1.5 ns – 2.5 ns – 2.5 ns – – 0.8 ns – ...
Page 26
... AT t RFC RRD 0 CLK + 7ns 14 t XSR 67 26 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 SDRAM -7E -75 Max Min Max Unit Notes – 5.4 5.4 ns – 5.4 6 – – 0.8 ns – – 1.5 ns – ...
Page 27
... PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN Electrical Specifications – AC Operating Conditions Symbol t BDL t CCD t CDL t CKED t DAL t DPL t DQD t DQM t DQZ t DWD t MRD t PED t RDL ROH(3) 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 SDRAM -6 Unit Notes 10 ...
Page 28
... V and V IL,max IH,min always be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09. t CKS. Clock(s) specified as a reference only at minimum cycle rate plus RP. Clock(s) specified as a reference only at minimum cycle rate. t WR. 28 256Mb: x4, x8, x16 SDRAM Symbol -7E -75 t BDL CCD CDL 1 ...
Page 29
... WRITE is executed for -75/- with no load is 4.6ns and is guaranteed by design. the first clock delay, after the last WRITE is executed. May not exceed limit set for pre- charge mode. 29 256Mb: x4, x8, x16 SDRAM t RP) begins at 7ns for -7E and t CKS = 3.0ns. t RP) begins 6ns for -6A after Micron Technology, Inc ...
Page 30
... Functional Description In general, 256Mb SDRAM devices (16 Meg banks, 8 Meg banks, and 4 Meg banks) are quad-bank DRAM that operate at 3.3V and include a synchronous interface. All signals are registered on the positive edge of the clock signal, CLK. Each of the x4’s 67,108,864-bit banks is organized as 8192 rows by 2048 columns by 4 bits. Each of the x8’ ...
Page 31
... However, the DQ column reads a “Don’t Care” state to illustrate that the BURST TERMINATE command can occur when there is no data present. charged and BA0, BA1 are “Don’t Care.” except for CKE. delay). 31 256Mb: x4, x8, x16 SDRAM ADDR ...
Page 32
... BA0, BA1 PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev MRD is met. HIGH CS# Row address Bank address Don’t Care 32 256Mb: x4, x8, x16 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. Commands ...
Page 33
... enable auto precharge, DIS AP = disable auto precharge. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN HIGH CS# Column address DIS AP Bank address 33 256Mb: x4, x8, x16 SDRAM Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. Commands ...
Page 34
... enable auto precharge, DIS AP = disable auto precharge. PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN HIGH CS# Column address DIS AP Bank address Valid address 34 256Mb: x4, x8, x16 SDRAM Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. Commands ...
Page 35
... RP) after the PRECHARGE command is issued. Input A10 determines HIGH CS# All banks Bank selected Bank address Valid address 35 256Mb: x4, x8, x16 SDRAM Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. Commands ...
Page 36
... SELF REFRESH The SELF REFRESH command can be used to retain data in the SDRAM, even if the rest of the system is powered-down. When in the self refresh mode, the SDRAM retains data without external clocking. ...
Page 37
... RP is met, the bank will be in the idle state. Row activating: Starts with registration of an ACTIVE command and ends when t met. After RCD is met, the bank will be in the row active state. 37 256Mb: x4, x8, x16 SDRAM is HIGH (see Table 19 (page 41 has been met. t RCD has been met ...
Page 38
... RP is met. After RP is met, all banks will be in the idle state. auto precharge enabled and READs or WRITEs with auto precharge disabled. valid state for precharging. gardless of bank. 38 256Mb: x4, x8, x16 SDRAM has been met. After has been met. After ...
Page 39
... Read: A READ burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. Write: A WRITE burst has been initiated, with auto precharge disabled, and has not yet terminated or been terminated. 39 256Mb: x4, x8, x16 SDRAM is HIGH (Table 19 (page 41)), and has been met. ...
Page 40
... WRITE to bank m will interrupt the WRITE on bank n when registered. The PRECHARGE to bank n will begin after to bank m is registered. The last valid WRITE to bank n will be data registered one clock to the WRITE to bank m. 40 256Mb: x4, x8, x16 SDRAM has been met. After has been met ...
Page 41
... Reading or writing H 1. CKE Notes: 2. Current state is the state of the SDRAM immediately prior to clock edge n. 3. COMMAND 4. All states and sequences not shown are illegal or reserved. 5. Exiting power-down at clock edge n will put the device in the all banks idle state in time 6. Exiting self refresh at clock edge n will put the device in the all banks idle state after 7 ...
Page 42
... After power is applied signal cycling within timing constraints specified for the clock pin), the SDRAM re- quires a 100μs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100μs period and continuing at least through the end of this period, COMMAND INHIBIT or NOP commands must be applied. After the 100μ ...
Page 43
... At this point the DRAM is ready for any valid command. Note: More than two AUTO REFRESH commands can be issued in the sequence. After steps 9 and 10 are complete, repeat them until the desired number of AUTO REFRESH + loops is achieved. PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, x8, x16 SDRAM 43 Micron Technology, Inc ...
Page 44
... RP t RFC Precharge AUTO REFRESH all banks 256Mb: x4, x8, x16 SDRAM LOAD MODE NOP NOP NOP ( ( REGISTER ) ) ( ( ) ) ( ( ) ) CODE ( ( ) ) ...
Page 45
... PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev MRD before initiating the subsequent operation. Violating either of these require- 45 256Mb: x4, x8, x16 SDRAM Mode Register Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 46
... Mode WB CAS Latency Operating Mode Standard Operation All other states reserved CAS Latency Reserved Reserved Reserved Reserved Reserved Reserved 256Mb: x4, x8, x16 SDRAM Mode Register Address Bus Mode Register (Mx) BT Burst Length Burst Length Reserved Reserved Reserved Full Page Burst Type ...
Page 47
... The ordering of accesses within a burst is determined by the burst length, the burst type, and the starting column address. PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, x8, x16 SDRAM 47 Micron Technology, Inc. reserves the right to change products or specifications without notice. Mode Register © 1999 Micron Technology, Inc. All rights reserved. ...
Page 48
... A1 select the starting column within the block. A0–A2 select the starting column within the block. (x16) select the starting column. ing access wraps within the block. accessed, and mode register bit M3 is ignored. 48 256Mb: x4, x8, x16 SDRAM Mode Register Order of Accesses Within a Burst Type = Interleaved 0-1 1-0 ...
Page 49
... PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev CLK READ NOP CLK READ NOP 256Mb: x4, x8, x16 SDRAM Mode Register T2 T3 NOP OUT NOP NOP OUT t AC Don’t Care Undefined Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 50
... Bank/Row Activation Before any READ or WRITE commands can be issued to a bank within the SDRAM, a row in that bank must be opened. This is accomplished via the ACTIVE command, which selects both the bank and the row to be activated. After a row is opened with the ACTIVE command, a READ or WRITE command can be ...
Page 51
... This is shown in Figure 22 (page 53) for CL2 and CL3. SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated with a prefetch architecture. A READ command can be initiated on any clock cycle following a READ command ...
Page 52
... Each READ command can be issued to any bank. DQM is LOW. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev CLK READ NOP NOP Bank, Col OUT CLK READ NOP NOP Bank, Col 256Mb: x4, x8, x16 SDRAM READ Operation NOP READ NOP NOP cycle Bank, Col OUT OUT OUT OUT NOP ...
Page 53
... CLK READ READ READ Bank, Bank, Bank, Col n Col a Col OUT CLK READ READ READ Bank, Bank, Bank, Col n Col a Col 256Mb: x4, x8, x16 SDRAM READ Operation READ NOP NOP Bank, Col OUT OUT OUT READ NOP NOP NOP Bank, Col ...
Page 54
... The READ command can be issued to any bank, and the WRITE command can be Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev READ NOP NOP Bank, Col n DQ Transitioning data to any bank burst of one is used, DQM is not required. 54 256Mb: x4, x8, x16 SDRAM READ Operation met. Note that part of T4 NOP WRITE Bank, Col OUT Don’ ...
Page 55
... Col n DQ Transitioning data to any bank CLK READ NOP NOP Bank a, Col OUT CLK READ NOP NOP Bank a, Col 256Mb: x4, x8, x16 SDRAM READ Operation NOP NOP WRITE Bank, Col OUT Don’t Care NOP PRECHARGE NOP NOP cycle Bank (a or all) ...
Page 56
... DQM is LOW. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev CLK READ NOP NOP Bank, Col OUT CLK READ NOP NOP Bank, Col 256Mb: x4, x8, x16 SDRAM READ Operation BURST NOP NOP NOP TERMINATE cycle OUT OUT OUT BURST NOP NOP NOP TERMINATE cycles D ...
Page 57
... For this example and Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev READ NOP ACTIVE t CMH Row Column m Row Bank 0 Bank OUT bank 0 57 256Mb: x4, x8, x16 SDRAM READ Operation NOP READ NOP 1 Column b Enable auto precharge Bank OUT OUT OUT bank 0 t RCD - bank bank 3 Don’ ...
Page 58
... RCD 1. For this example Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev READ NOP NOP NOP t CMH OUT t LZ All locations within same row CAS latency Full-page burst does not self-terminate. Can use BURST TERMINATE command. 58 256Mb: x4, x8, x16 SDRAM READ Operation NOP ...
Page 59
... PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev READ NOP NOP t CMH Column m Bank OUT 256Mb: x4, x8, x16 SDRAM READ Operation NOP NOP NOP OUT OUT Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. T8 NOP Don’ ...
Page 60
... Figure 31 (page 61)). Data either the last of a burst of two or the last desired data element of a longer burst. SDRAM devices use a pipelined architecture and therefore do not require the 2n rule associated with a prefetch architecture. A WRITE command can be initiated on any clock cycle following a previous WRITE command ...
Page 61
... Don’t Care least one clock with time to complete, regardless of frequency met. 61 256Mb: x4, x8, x16 SDRAM WRITE Operation t WR after the clock edge at Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 62
... Transitioning data CLK READ WRITE NOP Bank, Bank, Col n Col Transitioning data bank. DQM is LOW for illustration. 62 256Mb: x4, x8, x16 SDRAM WRITE Operation T3 WRITE Bank, Col Don’t Care NOP NOP NOP D D OUT OUT Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 63
... PRECHARGE Bank Bank all) Col < 15ns DQM WRITE NOP NOP Bank a, Col 256Mb: x4, x8, x16 SDRAM WRITE Operation NOP NOP NOP ACTIVE Bank a, Row t RP NOP NOP ACTIVE PRECHARGE Bank Bank all) Row t WR Transitioning data Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 64
... T1 T2 CLK BURST NEXT WRITE TERMINATE COMMAND Bank, Address Col Data IN Transitioning data Don’t Care 64 256Mb: x4, x8, x16 SDRAM WRITE Operation Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 65
... Rev WRITE NOP ACTIVE t CMH Row Row Bank RCD - bank 1 65 256Mb: x4, x8, x16 SDRAM WRITE Operation NOP WRITE NOP NOP Column b Enable auto precharge Bank bank bank 0 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 66
... AH BA0, BA1 Bank DQ t RCD 1. Notes: 2. Page left open; no PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev WRITE NOP NOP t CMH t CMS Column m Bank must be satisfied prior to issuing a PRECHARGE command. t RP. 66 256Mb: x4, x8, x16 SDRAM WRITE Operation NOP NOP ( ( ) ) ( ( ) ) ( ( ...
Page 67
... WRITE NOP t CMS t CMH Column m Enable auto precharge Disable auto precharge Bank 256Mb: x4, x8, x16 SDRAM WRITE Operation NOP NOP NOP Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. T7 NOP ...
Page 68
... Burst Type (page 47) section. Micron SDRAM supports concurrent auto precharge; cases of concurrent auto pre- charge for READs and WRITEs are defined below. READ with auto precharge interrupted by a READ (with or without auto precharge) A READ to bank m will interrupt a READ on bank n following the programmed CAS la- tency ...
Page 69
... READ - AP READ - AP NOP NOP Bank n Bank m Page active READ with burst of 4 Interrupt burst, precharge Page active READ with burst of 4 Bank n, Bank m, Col a Col (bank n) 69 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation NOP NOP NOP NOP Idle bank bank n Precharge D D ...
Page 70
... Rev READ - AP NOP NOP NOP Bank n READ with burst of 4 Page active Bank n, Col a D OUT (bank n) OUT 70 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation WRITE - AP NOP NOP NOP Bank m Interrupt burst, precharge bank bank n WRITE with burst of 4 Bank m, Col d D ...
Page 71
... RC 1. For this example and Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev READ NOP NOP t CMH Column m Bank OUT 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation NOP NOP NOP OUT OUT OUT Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 72
... For this example and the READ burst is followed by a manual PRECHARGE. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev READ NOP NOP t CMS t CMH Column m Bank OUT 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation NOP PRECHARGE NOP All banks Single bank Bank( OUT OUT OUT Don’ ...
Page 73
... NOP t CMS t CMH Column m Enable auto precharge Bank 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation T5 T6 NOP NOP t OH OUT t RP Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 74
... CH READ NOP NOP t CMS t CMH Column m Bank OUT 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation PRECHARGE NOP ACTIVE Row All banks Row Single bank Bank(s) Bank t RP Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 75
... Bank m, Col a Col WRITE - AP NOP NOP NOP Bank n Page active WRITE with burst of 4 Page active Bank n, Col 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation NOP NOP NOP NOP Precharge bank bank OUT OUT (bank m) Don’t Care WRITE - AP NOP NOP NOP ...
Page 76
... WRITE NOP NOP t CMH Bank 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation NOP NOP NOP NOP Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. T9 ACTIVE Row Row Bank Don’t Care ...
Page 77
... CH WRITE NOP NOP NOP t CMH Bank 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation NOP PRECHARGE NOP All banks Single bank Bank Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. T9 ACTIVE ...
Page 78
... WRITE NOP NOP t CMS t CMH Column m Bank 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation NOP NOP ACTIVE Row Row Bank t RP Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. T8 NOP Don’t Care ...
Page 79
... WRITE NOP NOP t CMS t CMH Column m Bank 256Mb: x4, x8, x16 SDRAM PRECHARGE Operation PRECHARGE NOP ACTIVE All banks Row Single bank Bank Bank t RP Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 80
... REFRESH command. After the AUTO REFRESH command is initiated, it must not be interrupted by any exe- cutable command until NOP commands must be issued on each positive edge of the clock. The SDRAM re- quires that every row be refreshed each REFRESH command—calculated by dividing the refresh period ( rows to be refreshed—meets the timing requirement and ensures that each row is re- freshed ...
Page 81
... RFC 81 256Mb: x4, x8, x16 SDRAM AUTO REFRESH Operation AUTO NOP NOP ( ( REFRESH ) ) ( ( ) ) ( ( ) ) ( ( ) ) ( ( ) ...
Page 82
... Upon exiting the self refresh mode, AUTO REFRESH commands must be issued accord- ing to the distributed refresh rate ( AUTO REFRESH utilize the row refresh counter. PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev. N 1/10 EN 256Mb: x4, x8, x16 SDRAM SELF REFRESH Operation t RAS and remains in self refresh mode for t ...
Page 83
... Enter self refresh mode CLK stable prior to exiting self refresh mode not required. 83 256Mb: x4, x8, x16 SDRAM SELF REFRESH Operation NOP REFRESH ( ( ) ) ( ( ) ) ( ...
Page 84
... All banks idle, enter active banks power-down mode 1. Violating refresh requirements during power-down may result in a loss of data. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev CKS NOP NOP Input buffers gated off while in power-down mode 84 256Mb: x4, x8, x16 SDRAM t CKS CKS ( ( ) ...
Page 85
... For this example greater, and DQM is LOW. PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev NOP WRITE Bank, Col 256Mb: x4, x8, x16 SDRAM Clock Suspend NOP NOP Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. © 1999 Micron Technology, Inc. All rights reserved. ...
Page 86
... For this example greater, and DQM is LOW. Note: PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev READ NOP NOP Bank, Col n D OUT 86 256Mb: x4, x8, x16 SDRAM Clock Suspend NOP NOP NOP OUT OUT OUT Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 87
... Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef8091e6d1 256Mb_sdr.pdf - Rev CKH NOP NOP OUT t LZ times occur. 87 256Mb: x4, x8, x16 SDRAM Clock Suspend NOP NOP WRITE Column e Bank OUT IN Don’t Care Micron Technology, Inc. reserves the right to change products or specifications without notice. ...