MT41J256M4HX-187E:D Micron Technology Inc, MT41J256M4HX-187E:D Datasheet - Page 185
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MT41J256M4HX-187E:D
Manufacturer Part Number
MT41J256M4HX-187E:D
Description
Manufacturer
Micron Technology Inc
Type
DDR3 SDRAMr
Datasheet
1.MT41J256M4HX-187ED.pdf
(208 pages)
Specifications of MT41J256M4HX-187E:D
Organization
256Mx4
Density
1Gb
Address Bus
17b
Maximum Clock Rate
1.066GHz
Operating Supply Voltage (typ)
1.5V
Package Type
FBGA
Operating Temp Range
0C to 95C
Operating Supply Voltage (max)
1.575V
Operating Supply Voltage (min)
1.425V
Supply Current
190mA
Pin Count
78
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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RESET Operation
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf – Rev. J 05/10 EN
The RESET signal (RESET#) is an asynchronous signal that triggers any time it drops
LOW, and there are no restrictions about when it can go LOW. After RESET# goes LOW,
it must remain LOW for 100ns. During this time, the outputs are disabled, ODT (R
turns off (High-Z), and the DRAM resets itself. CKE should be brought LOW prior to RE-
SET# being driven HIGH. After RESET# goes HIGH, the DRAM must be reinitialized as
though a normal power-up was executed. All refresh counters on the DRAM are reset,
and data stored in the DRAM is assumed unknown after RESET# has gone LOW.
185
Micron Technology, Inc. reserves the right to change products or specifications without notice.
1Gb: x4, x8, x16 DDR3 SDRAM
© 2006 Micron Technology, Inc. All rights reserved.
RESET Operation
TT
)
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