MT29F2G16ABAEAWP-IT:E Micron Technology Inc, MT29F2G16ABAEAWP-IT:E Datasheet
MT29F2G16ABAEAWP-IT:E
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MT29F2G16ABAEAWP-IT:E Summary of contents
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... NAND Flash Memory MT29F2G08ABAEAH4, MT29F2G08ABAEAWP, MT29F2G08ABBEAH4 MT29F2G08ABBEAHC, MT29F2G16ABAEAWP, MT29F2G16ABBEAH4 MT29F2G16ABBEAHC Features • Open NAND Flash Interface (ONFI) 1.0-compliant • Single-level cell (SLC) technology • Organization – Page size x8: 2112 bytes (2048 + 64 bytes) – Page size x16: 1056 words (1024 + 32 words) – Block size: 64 pages (128K + 4K bytes) – ...
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... Part Numbering Information Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type, visit www.micron.com/products. Contact the factory for devices not found. Figure 1: Marketing Part Number Chart ...
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... ERASE BLOCK (60h-D0h) ............................................................................................................................ 70 ERASE BLOCK TWO-PLANE (60h-D1h) ....................................................................................................... 71 Internal Data Move Operations ....................................................................................................................... 72 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Features ...
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... Rev. B, Advance – 9/09 ............................................................................................................................... 124 Rev. A, Advance – 7/09 ............................................................................................................................... 124 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. Features ...
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... Table 29: AC Characteristics: Normal Operation (1.8V) .................................................................................. 109 Table 30: Program/Erase Characteristics ....................................................................................................... 111 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2009 Micron Technology, Inc. All rights reserved. ...
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... Figure 5: 48-Pin TSOP – Type 1, CPL .............................................................................................................. 12 Figure 6: 63-Ball VFBGA (10.5mm x 13mm) .................................................................................................... 13 Figure 7: 63-Ball VFBGA (9mm x 11mm) ......................................................................................................... 14 Figure 8: NAND Flash Die (LUN) Functional Block Diagram ........................................................................... 15 Figure 9: Array Organization – MT29F2G08 (x8) .............................................................................................. 16 Figure 10: Array Organization – MT29F2G16 (x16) .......................................................................................... 17 Figure 11: Asynchronous Command Latch Cycle ............................................................................................ 19 Figure 12: Asynchronous Address Latch Cycle ...
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... Figure 52: PROGRAM FOR INTERNAL DATA MOVE (85h–10h) Operation ....................................................... 74 Figure 53: PROGRAM FOR INTERNAL DATA MOVE (85h-10h) with RANDOM DATA INPUT (85h) .................. 75 Figure 54: PROGRAM FOR INTERNAL DATA MOVE TWO-PLANE (85h-11h) Operation ................................... 75 Figure 55: Flash Array Protected: Invert Area Bit = 0 ........................................................................................ 77 Figure 56: Flash Array Protected: Invert Area Bit = 1 ........................................................................................ 77 Figure 57: UNLOCK Operation ...................................................................................................................... 78 Figure 58: LOCK Operation ...
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... NAND Flash die. A NAND Flash die is the minimum unit that can independently execute commands and report status. A NAND Flash die, in the ONFI specification, is referred logical unit (LUN). There is at least one NAND Flash die per chip enable signal. For further details, see Device and Array Organization. ...
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... PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/ Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Signal Assignments x8 x16 48 Vss 1 Vss 47 DNU I/O15 46 NC I/O14 45 NC I/O13 44 I/O7 I/O7 43 I/O6 I/O6 42 I/O5 I/O5 41 I/O4 I/O4 ...
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... For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V device. Notes: 2. These pins might not be bonded in the package; however, Micron recommends that the customer connect these pins to the designated external sources for ONFI compatibility. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory ...
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... Figure 4: 63-Ball VFBGA, x16 (Balls Down, Top View For the 3V device, G5 changes to DNU. NO LOCK function is available on the 3.3V device. Note: PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory WP# ALE Vss CE# WE# R/B# Vcc RE# CLE Vss DNU Vcc LOCK ...
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... All dimensions are in millimeters. Note: PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory 20.00 ±0.25 18.40 ±0. See detail A 1.20 MAX 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. Package Dimensions ...
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... Bottom side saw fiducials may or 10.5 ±0.1 may not be covered with soldermask. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Package Dimensions Ball A1 ID 1.0 MAX 0.25 MIN © 2009 Micron Technology, Inc. All rights reserved. ...
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... Ball ±0 0.8 TYP 7.2 CTR 9 ±0.1 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Package Dimensions Ball A1 ID 1.0 MAX 0.25 MIN © 2009 Micron Technology, Inc. All rights reserved. ...
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... The addresses are latched by an address register and sent to a row decoder to select a row address column decoder to select a column address. Data is transferred to or from the NAND Flash memory array, byte by byte (x8) or word by word (x16), through a data register and a cache register. ...
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... LOW LOW PA5 PA4 BA13 BA12 LOW LOW 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Device and Array Organization DQ7 DQ0 1 page = ( bytes) 1 block = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 plane = (128K + 4K) bytes x 1024 blocks ...
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... PA5 PA4 BA14 BA13 BA12 LOW LOW LOW 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Device and Array Organization DQ15 DQ0 1 page = ( words) 1 block = (1K + 32) words x 64 pages = (64K + 2K) words 1 plane = (64K + 2K) words x 1024 blocks ...
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... This helps reduce power con- sumption. The CE# “Don’t Care” operation enables the NAND Flash to reside on the same asyn- chronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus ...
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... Figure 11: Asynchronous Command Latch Cycle CLE CE# WE# ALE I/Ox PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Bus Operation t t CLS CLH ALS ALH COMMAND 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... ALS t ALH Col Col Row add 1 add 2 add 1 20 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Row Row add 2 add 3 Don’t Care Undefined © 2009 Micron Technology, Inc. All rights reserved. ...
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... ALE I/Ox PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN Asynchronous Interface Bus Operation M Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t CLH © 2009 Micron Technology, Inc. All rights reserved. Don’t Care ...
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... Asynchronous Data Output Data can be output from a die (LUN READY state. Data output is supported following a READ operation from the NAND Flash array. Data is output from the cache register of the selected die (LUN) to I/O[7:0] on the falling edge of RE# when CE# is LOW, ALE is LOW, CLE is LOW, and WE# is HIGH. ...
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... RP t REH t REA t REA t RLOH D D OUT OUT 23 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t CHZ t COH t RHZ t RHOH D OUT Don’t Care before issu- © 2009 Micron Technology, Inc. All rights reserved. ...
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... The minimum value for Rp is determined by the output drive capability of the R/B# signal, the output voltage swing, and V Where Σ Figure 16: READ/BUSY# Open Drain PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Bus Operation × (MAX (MAX ...
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... Fall t Rise – Rise calculated at 10% and 90% points Fall - Rise are calculated at 10% and 90% points. 25 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory 3. Rise 1.8V CC © 2009 Micron Technology, Inc. All rights reserved. ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory 8000 10,000 12,000 Rp (Ω (MAX 6000 8000 10,000 Rp (Ω © 2009 Micron Technology, Inc. All rights reserved. ...
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... Asynchronous Interface Bus Operation 1200 1000 800 600 400 200 0 0 2000 4000 27 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory 6000 8000 10,000 12,000 (MAX) Rp (Ω 100pF © 2009 Micron Technology, Inc. All rights reserved. ...
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... The RESET (FFh) command must be the first command issued to all targets (CE#s) after the NAND Flash device is powered on. Each target will be busy for 1ms after a RESET command is issued. The RESET busy time can be monitored by polling issuing the READ STATUS (70h) command to poll the status register. ...
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... ERASE BLOCK 60h Internal Data Move Operations READ FOR INTERNAL 00h DATA MOVE PROGRAM FOR INTER- 85h NAL DATA MOVE PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Number of Valid Data Address Input Command Cycles Cycles Cycle #2 – ...
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... Cycle #2 Cycles 5 00h 5 5 00h 5 – 5 E0h 30 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Command Definitions Valid While Valid While Selected LUN Other LUNs 1 Cycle #2 is Busy are Busy – No Yes – ...
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... D1h-60h 31 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Command Definitions Com- Valid While Valid While mand Selected Other LUNs Cycle #3 LUN is Busy are Busy 10h No Yes ...
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... The RESET command must be issued to all CE#s as the first command after power-on. The device will be busy for a maximum of 1ms. Figure 23: RESET (FFh) Operation Cycle type I/O[7:0] R/B# PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory t RST after the RESET command is written to the Command ...
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... See the READ ID Parameter tables for byte definitions. Note: Figure 25: READ ID (90h) with 20h Address Operation Cycle type I/O[7:0] 1. See READ ID Parameter tables for byte definitions. Note: PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Command Address D OUT t WHR 90h 00h ...
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... Byte value MT29F2G08ABBEA MT29F2G16ABBEA MT29F2G08ABAEA MT29F2G16ABAEA Byte 4 ECC level 4-bit ECC/512 (main (spare (pari- ty)bytes Planes per CE# 2 Plane size 1Gb PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory READ ID Parameter Tables I/07 I/06 I/05 I/04 I/ ...
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... MT29F2G08ABAEA MT29F2G16ABAEA binary hexadecimal. Note: Table 8: READ ID Parameters for Address 20h Byte Options I/07 “O” “N” “F” “I” Undefined hexadecimal. Note: PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory I/07 I/06 I/ I/06 I/05 I/04 I/ ...
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... Cycle type Command Address I/O[7:0] ECh R/B# PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/ OUT 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory READ PARAMETER PAGE (ECh OUT OUT OUT OUT P1 … © 2009 Micron Technology, Inc. All rights reserved. ...
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... MT29F2G16ABAEA3W 19h, 00h MT29F2G16ABBEA3W 19h, 00h MT29F2G08ABBEAH4 18h, 00h MT29F2G16ABBEAH4 19h, 00h MT29F2G08ABAEAWP 18h, 00h MT29F2G16ABAEAWP 19h, 00h MT29F2G08ABAEAH4 18h, 00h MT29F2G08ABBEAHC 18h, 00h MT29F2G16ABBEAHC 19h, 00h 3Fh, 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, ...
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... MT29F2G16ABAEAWP 4Dh, 54h, 32h, 39h, 46h, 32h, 47h, 31h, 36h, 41h, 42h, 41h, 45h, 41h, 57h, 50h, 20h, 20h, 20h, 20h ...
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... MT29F2G08ABBEA3W 1Fh, 00h MT29F2G16ABAEA3W 3Fh, 00h MT29F2G16ABBEA3W 1Fh, 00h MT29F2G08ABBEAH4 1Fh, 00h MT29F2G16ABBEAH4 1Fh, 00h MT29F2G08ABAEAWP 3Fh, 00h MT29F2G16ABAEAWP 3Fh, 00h MT29F2G08ABAEAH4 3Fh, 00h MT29F2G08ABBEAHC 1Fh, 00h MT29F2G16ABBEAHC 1Fh, 00h 58h, 02h B8h, 0Bh 19h, 00h 64h, 00h 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, 00h, ...
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... Additional redundant parameter pages hexadecimal. Note: PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Parameter Page Data Structure Tables 1 Value 01h, 00h, 00h, 02h, 04h, 80h, 01h, 81h, 04h, 01h, 02h, 01h,0Ah, 00h, 00h, 00h, 00h, 00h, 00h, 00h, ...
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... Cycle type Command Address I/O[7:0] EDh R/B# PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/ OUT 00h Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory READ UNIQUE ID (EDh OUT OUT OUT OUT U1 … © 2009 Micron Technology, Inc. All rights reserved. ...
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... The sequence to disable internal ECC with SET FEATURES is EFh(cmd)-90h(addr)- 00h(data)-00h(data)-00h(data)-00h(data)-wait( is EEh. Table 10: Feature Address Definitions Feature Address PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Definition 00h Reserved 01h Timing mode 02h–7Fh ...
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... Reserved (0) 0 Reserved (0) 1 Reserved (0) Reserved (0) Reserved (0) Command Address ADL I/O[7:0] EFh FA P1 R/B# 43 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Feature Operations I/O2 I/O1 I/O0 Value 0 00h 1 01h 1 1 03h 00h 0 0 ...
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... After FEAT completes, the host enables data output mode to read the subfeature param- eters. Figure 29: GET FEATURES (EEh) Operation Cycle type I/Ox R/B# PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Command Address EEh FEAT Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... Supported timing modes are reported in the parame- ter page. 2. Supported for both 1.8V and 3.3V. 3. Supported for 3.3V only. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory I/O7 I/O6 I/O5 I/O4 I/O3 Reserved (0) ...
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... This feature address is used to change the default R/B# pull-down strength. Its strength Note: should be selected based on the expected loading of R/B#. Full strength is the default, power-on value. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory I/O7 I/O6 I/O5 I/O4 I/O3 ...
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... I/O[7:0] as long as CE# and RE# are LOW not necessary to toggle RE# to see the status register update. While monitoring the status register to determine when a data transfer from the Flash array to the data register ( command to disable the status register and enable data output (see Read Operations). ...
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... Use of the READ STATUS ENHANCED (78h) command is prohibited during the power- on RESET (FFh) command and when OTP mode is enabled also prohibited follow- ing some of the other reset, identification, and configuration operations. See individual operations for specific details. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Command D OUT t WHR ...
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... Figure 31: READ STATUS ENHANCED (78h) Operation Cycle type I/Ox PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Command Address Address Address t WHR 78h Micron Technology, Inc. reserves the right to change products or specifications without notice. Status Operations D OUT SR © 2009 Micron Technology, Inc. All rights reserved. ...
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... Rev. H 09/10 EN Command Address Address Command t RHW 05h Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Column Address Operations D D OUT OUT t WHR E0h © 2009 Micron Technology, Inc. All rights reserved. ...
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... WHR before requesting data output. The selected die (LUN) Address Address Address Address Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Column Address Operations Address Command D OUT t WHR R3 E0h Dk © 2009 Micron Technology, Inc. All rights reserved. ...
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... I/O[7:0] Dn RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/ Command Address Address 85h Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Column Address Operations t ADL before inputting data. As defined for PAGE (CACHE) PROGRAM ADL © ...
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... The PROGRAM FOR INTERNAL DATA INPUT (85h) command changes the row address (block and page) where the cache register contents will be programmed in the NAND Flash array. It also changes the column address of the selected cache register and ena- bles data input on the specified die (LUN). This command is accepted by the selected die (LUN) when it is ready (RDY = 1 ...
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... RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN Command Address Address Address Address 85h Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Column Address Operations As defined for PAGE (CACHE) PROGRAM Address ADL © 2009 Micron Technology, Inc. All rights reserved. ...
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... NAND Flash array to the data register. To begin a read page cache sequence, begin by reading a page from the NAND Flash array to its corresponding cache register using the READ PAGE (00h-30h) command. ...
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... Two-Plane Read Cache Operations Two-plane read cache operations can be used to output data from more than one cache register while concurrently copying one or more pages from the NAND Flash array to the data register. This is done by prepending READ PAGE TWO-PLANE (00h-00h-30h) commands in front of the PAGE READ CACHE RANDOM (00h-31h) command. ...
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... The READ PAGE (00h-30h) command is used as the final command of a two-plane read operation preceded by one or more READ PAGE TWO-PLANE (00h-00h-30h) com- mands. Data is transferred from the NAND Flash array for all of the addressed planes to their respective cache registers. When the die (LUN) is ready (RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the plane addressed in the READ PAGE (00h-30h) command ...
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... RCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register ...
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... ARDY = 0) for busy with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified page is copying from the NAND Flash array to the data register. At this point, data can be output from the cache register beginning at column address 0. The RANDOM DATA READ (05h-E0h) command can be used to change the column address of the data being output from the cache register ...
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... Command D OUT 31h RCBSY t RR Page N 60 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Read Operations OUT OUT OUT D0 … RCBSY t RR Page M © 2009 Micron Technology, Inc. All rights reserved. ...
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... RCBSY, R/B# goes HIGH and the die (LUN Command OUT OUT OUT … D 3Fh Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Read Operations D D OUT OUT D0 … RCBSY RR Page N © 2009 Micron Technology, Inc. All rights reserved. D ...
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... READ PAGE TWO-PLANE 00h-00h-30h The READ PAGE TWO-PLANE (00h-00h-30h) operation is similar to the PAGE READ (00h-30h) operation. It transfers two pages of data from the NAND Flash array to the data registers. Each page must be from a different plane on the same die. To enter the READ PAGE TWO-PLANE mode, write the 00h command to the command register, and then write five address cycles for plane 0 (BA6 = 0) ...
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... Col Row Row Row 06h D OUT add 1 add 2 add 1 add 2 add 3 Plane 1 address 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Read Operations Row Row Row 30h add 1 add 2 add Plane 1 address E0h ...
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... The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE TWO-PLANE (80h-11h) command, programs one page from the cache register to the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that the operation has completed successfully. ...
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... PROG_ECC, the internal ECC generates parity bits when error detection is com- Address Address Address ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Program Operations Command Command IN IN … Dn 10h 70h t PROG PROG_ECC © ...
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... It is preceded by one or more PROGRAM PAGE TWO- PLANE (80h-11h) commands. Data for all of the addressed planes is transferred from the cache registers to the corresponding data registers, then moved to the NAND Flash array. The host should check the status of the operation by using the status operations (70h, 78h) ...
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... D0 Address Address Address ADL Address Address Address IN t ADL Address Address Address ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Program Operations Command … Dn 15h CBSY Command … Dn 15h CBSY Command IN IN ...
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... NAND Flash array. This command is accepted by the die (LUN) when it is ready (RDY = 1). To input a page to the cache register and queue moved to the NAND Flash array at the block and page address specified, write 80h to the command register. Unless this command has been preceded by a PROGRAM PAGE TWO-PLANE (80h-11h) command, issuing the 80h to the command register clears all of the cache registers' contents on the selected target ...
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... Figure 45: PROGRAM PAGE TWO-PLANE (80h–11h) Operation Cycle type Command Address Address I/O[7:0] 80h C1 C2 RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory D Address Address Address IN t ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... Erase Operations Erase operations are used to clear the contents of a block in the NAND Flash array to prepare its pages for program operations. Erase Operations The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK TWO- PLANE (60h-D1h) command, erases one block in the NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify that this operation completed successfully ...
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... ERASE BLOCK TWO-PLANE (60h-D1h) The ERASE BLOCK TWO-PLANE (60h-D1h) command queues a block in the specified plane to be erased in the NAND Flash array. This command can be issued one or more times. Each time a new plane address is specified, that plane is also queued for a block to be erased. To specify the final block to be erased and to begin the ERASE operation for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command ...
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... PROGRAM FOR INTERNAL DATA MOVE operations by enabling movement of multiple pages from the cache registers to different planes of the NAND Flash array. This is done by prepending one or more PROGRAM FOR INTER- NAL DATA MOVE (85h-11h) commands in front of the PROGRAM FOR INTERNAL DATA MOVE (85h-10h) command ...
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... R2 R3 Address Address Address Address Command Address Command D OUT t WHR C2 E0h Dk 73 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Internal Data Move Operations Command D D OUT OUT 35h n OUT OUT 35h D0 … ...
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... SR bit READ error Address Address Address Address Address Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Internal Data Move Operations t PROG_ECC Address 85h 10h 70h Status (5 cycles) Destination address SR bit READ successful SR bit READ error ...
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... Address Address Address Address Address Address WHR Address Address Address ADL Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Internal Data Move Operations WHR Command 10h PROG D D Command Command IN IN … Dn 11h DBSY © ...
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... The previ- ous unlocked block address range is not retained. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Block Lock Feature 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... Figure 55: Flash Array Protected: Invert Area Bit = 0 Block 2047 Block 2046 Block 2045 Block 2044 Block 2043 Block 2042 Block 2041 Block 2040 Block 2039 . . . . . . . . . . . . . . Block 0002 Block 0001 Block 0000 Figure 56: Flash Array Protected: Invert Area Bit = 1 Block 2047 Block 2046 ...
Page 78
... Invert area bit is applicable for 24h command; it may be LOW or HIGH for 23h command. Figure 57: UNLOCK Operation WP# CLE CE# WE# ALE RE# I/Ox R/B# PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory I/O6 I/O5 I/O4 I/O3 BA6 LOW LOW LOW BA14 BA13 BA12 ...
Page 79
... Figure 58: LOCK Operation CLE CE# WE# I/Ox PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Ah LOCK command 79 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Block Lock Feature © 2009 Micron Technology, Inc. All rights reserved. ...
Page 80
... LOCK (2Ah) command had been issued. The LOCK TIGHT (2Ch) command is disabled if LOCK is LOW at power-on. Figure 59: LOCK TIGHT Operation PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory t LBSY. The PROGRAM or ERASE operation does not LOCK WP# ...
Page 81
... X X CLE CE# WE# ALE RE# 7Ah Add 1 Add 2 Add 3 I/Ox BLOCK LOCK Block address READ STATUS 81 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Block Lock Feature t LBSY 70h READ STATUS I/O2 (Lock#) I/O1 (LT ...
Page 82
... LOCK Cmd UNLOCK Cmd with invert area bit = 1 UNLOCK Cmd with invert area bit = 0 82 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Block Lock Feature Power-up with LOCK LOW (default) BLOCK LOCK function ...
Page 83
... One-Time Programmable (OTP) Operations This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Thirty full pages (2112 bytes per page) of OTP data are available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area any way they choose ...
Page 84
... Status Operations). Each OTP page can be programmed to 8 partial-page programming. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory One-Time Programmable (OTP) Operations 84 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 85
... OTP address 1 x8 device 2112 bytes x16 device 1056 words 85 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory PROG 10h 70h PROGRAM READ STATUS command command OTP data written (following good status confirmation) © ...
Page 86
... OTP operation mode. Bit 5 of the status register reflects the state of R/B#. When the device is ready, read bit 0 of the status register to determine whether the oper- ation passed or failed (see Status Operations). PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory One-Time Programmable (OTP) Operations t t ADL ...
Page 87
... D page 00h IN PROGRAM command OTP address 87 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory PROG 10h 70h READ STATUS command OTP data protected © 2009 Micron Technology, Inc. All rights reserved. ...
Page 88
... One-Time Programmable (OTP) Operations t R) while the data is moved from the OTP page to the data register. The Col OTP 00h 00h 1 page OTP address 88 2Gb: x8, x16 NAND Flash Memory OUT OUT 30h Busy Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 89
... 00h 00h 30h OUT Busy 89 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t CLR t WHR t REA D Col Col OUT 05h E0h add 1 add 2 Column address m © 2009 Micron Technology, Inc. All rights reserved. ...
Page 90
... Two-Plane Operations Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each plane contains a cache register and a data register independent of the other planes. The planes are addressed via the low-order block address bits. Specific details are provided in Device and Array Organization. ...
Page 91
... Row Row D 06h OUT add 1 add 2 add 1 add 2 Plane 1 address 91 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Two-Plane Operations Page address M Col Row Row Row 30h add 1 add 2 add 3 Plane 1 address Row ...
Page 92
... Plane 1 data t DBSY input 11h 80h Address (5 cycles) 2nd-plane address 92 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Two-Plane Operations Address 05h E0h Data output (2 cycles) Plane 0 data E0h Data output Plane 1 data ...
Page 93
... Unlimited number of repetitions t PROG input 10h 93 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Two-Plane Operations t DBSY 11h 80h Address (5 cycles) Data input 2nd-plane address © ...
Page 94
... R/B# 80h Address/data input I/Ox 1st plane 1 R/B# 80h Address/data input I/Ox 1st plane 2 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory t DBSY 11h 80h Address/data input 2nd plane t DBSY 11h 80h Address/data input 2nd plane t DBSY ...
Page 95
... Address (5 cycles) 35h 2nd-plane source t PROG 10h 70h Status 95 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Two-Plane Operations t DBSY 85h Address (5 cycles) 11h 1st-plane destination © 2009 Micron Technology, Inc. All rights reserved. 1 ...
Page 96
... Optional t DBSY 85h Address (5 cycles) 2nd-plane destination 96 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Two-Plane Operations 06h Address (5 cycles) 2nd-plane source address Data output Data from 2nd-plane source from new column address ...
Page 97
... Data Address (2 cycles) Data Optional Unlimited number of repetitions 97 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Two-Plane Operations 85h Data Address (2 cycles) Data Optional Unlimited number of repetitions t PROG 70h Status © ...
Page 98
... Rev. H 09/ DBSY Address input (3 cycles) D1h 60h 2nd plane Optional Address (3 cycles) 98 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Two-Plane Operations t BERS D0h 70h Status or 78h WHR t REA Status output © ...
Page 99
... This is because the 80h command clears the cache register contents of all cache regis- ters on all planes. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Interleaved Die (Multi-LUN) Operations 99 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 100
... Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, the following precautions are required: • Always check status after a PROGRAM or ERASE operation • ...
Page 101
... Minimum ECC with internal ECC enabled Minimum required ECC for block 0 if PROGRAM/ ERASE cycles are less than 1000 PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Requirement 4-bit ECC per 516 bytes (user data bytes (parity data) 1-bit ECC per 528 bytes 101 Micron Technology, Inc ...
Page 102
... No 837h 834h Yes 83Fh 838h Yes PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Internal ECC and Spare Area Mapping for ECC Area Description Main 0 User data Main 1 User data Main 2 User data Main 3 User data Reserved User metadata II ...
Page 103
... No 41Bh 41Ah Yes 41Fh 41Ch Yes PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Internal ECC and Spare Area Mapping for ECC Area Description Main 0 User data Main 1 User data Main 2 User data Main 3 User data Reserved User metadata II ...
Page 104
... NVB during the endurance life of the device. Do not erase or program blocks marked invalid by the factory. 2. Block 00h (the first block) is guaranteed to be valid with ECC when shipped from the factory. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory SS Symbol 1. ...
Page 105
... Input pulse levels Input rise and fall times Input and output timing levels Output load Output load Note: 1. Verified in device characterization, not 100% tested. PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Symbol 25° MHz; Vin = 0V 1.8V 3 ...
Page 106
... R/B pull-down strength is not set to full. and V may need to be relaxed if I/O drive strength is not set to full 106 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Typ Max Unit – – ...
Page 107
... IH WP# – V –0 –100µ +100µ 0.2V I (R/B and 107 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Typ Max Unit – – – – – – µA – – 10 per die mA – ...
Page 108
... 100 t ADL begins in the address cycle on the final rising edge of WE#, and ends 108 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Conditions Max Unit – ns – ns – ns – ns – ns – ns – ns – ...
Page 109
... RST WHR Symbol CEA t CHZ t CLR t COH REA t REH t RHOH t RHW 109 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Conditions Min Max Unit – – – – – – – – – ...
Page 110
... Rev. H 09/10 EN Electrical Specifications – AC Characteristics and Operating Symbol t RHZ t RLOH RST WHR 110 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Conditions Min Max Unit – – – – – 5/10/500 µ ...
Page 111
... Typical is nominal voltage and room temperature. 5. Typical 6. Data transfer from Flash array to data register with internal ECC disabled characteristics may need to be relaxed if I/O drive strength is not set to full. 8. Typical program time is defined as the time within which more than 50% of the pages are programmed at nominal voltage and room temperature ...
Page 112
... CE WE# R/B# FFh I/O[7:0] RESET command Figure 81: READ STATUS Cycle CLE CE# WE# RE# I/O[7:0] PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Timing Diagrams t RST t CLR t CLS t CLH CEA t WHR 70h 112 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 113
... ALH t ALS Row add 1 Row add 2 Row add R_ECC 113 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory CEA t ALH WHR t REA Status output P255 © 2009 Micron Technology, Inc. All rights reserved. ...
Page 114
... CLE CE WE# ALE RE# Col Col I/Ox 00h add 1 add 2 RDY PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Timing Diagrams R_ECC Row Row Row 30h add 1 add 2 add 3 114 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 115
... Figure 85: READ PAGE Operation with CE# “Don’t Care” CLE CE# RE# ALE RDY WE# I/Ox 00h Address (5 cycles) PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory Asynchronous Interface Timing Diagrams R_ECC 30h t CEA CE REA CHZ t RE# COH Out I/Ox 115 Micron Technology, Inc ...
Page 116
... Col D 05h OUT OUT add 1 add 2 N Column address M 116 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t CLR t WHR t REA D D E0h OUT OUT © 2009 Micron Technology, Inc. All rights reserved. ...
Page 117
... REA t DH Dout Dout Dout 0 1 Page address t RCBSY Column address 0 117 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t CEA REA t RR Dout Dout 31h Dout 0 1 Page address t RCBSY M Column address 0 ...
Page 118
... DH t REA Dout Dout 31h RCBSY Page address M Column address 0 118 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Col Col Row Row 00h add 1 add 2 add 1 add 2 Column address Page address 00h N ...
Page 119
... Row Row Row IN IN add 1 add 2 add byte serial Input 119 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Byte 2 Byte 3 Byte WHR PROG or t PROG_ECC 10h 70h © 2009 Micron Technology, Inc. All rights reserved. ...
Page 120
... Row D D Col 85h IN IN add 3 add 1 add CHANGE WRITE Column address Serial input COLUMN command 120 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory Data input t ADL t PROG PROG_ECC D Col D IN 10h IN Q ...
Page 121
... Col Row Row 15h 70h Status 80h M add 1 add 2 add 1 add 2 Last page 121 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t ADL LPROG Row Row Row Din Din 10h add 1 add 2 add 3 ...
Page 122
... Busy D 70h Status 00h OUT D is optional OUT 122 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t ADL PROG Row Row Data Data 10h add 2 add READ STATUS ...
Page 123
... Destination address OUT t WB BERS t Row D0h add 3 Busy 123 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2Gb: x8, x16 NAND Flash Memory t PROG_ECC Address Address Data 85h Data 10h (5 cycles) (2 cycles) Column address 1, 2 (Unlimitted repetitions are possible) ...
Page 124
... Updated Boot Block Operation to include dual-plane restrictions • Added • Added note for gram/Erase Characteristics • Moved note from Rev. A, Advance – 7/09 • Initial release PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory R_ECC t RCBSY spec to Electrical Specifications - Program/Erase Characteristics t t ...
Page 125
... This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization some- PDF: 09005aef83b83f42 m69a_2gb_nand.pdf – Rev. H 09/10 EN 2Gb: x8, x16 NAND Flash Memory times occur. 125 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...