MT45W4MW16BBB-708 WT Micron Technology Inc, MT45W4MW16BBB-708 WT Datasheet - Page 36
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MT45W4MW16BBB-708 WT
Manufacturer Part Number
MT45W4MW16BBB-708 WT
Description
Manufacturer
Micron Technology Inc
Datasheet
1.MT45W4MW16BBB-708_WT.pdf
(61 pages)
Specifications of MT45W4MW16BBB-708 WT
Operating Temperature (max)
85C
Mounting
Surface Mount
Operating Temperature Classification
Commercial
Lead Free Status / RoHS Status
Compliant
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Table 17:
PDF: 09005aef80be1fbd/Source: 09005aef80be2036
Burst CellularRAM_2.fm - Rev. G 10/05 EN
Parameter
CE# HIGH between Subsequent Mixed-Mode
Operations
Minimum CE# Pulse Width
CE# LOW to WAIT Valid
Clock Period
CE# Setup to CLK Active Edge
Hold Time from Active CLK Edge
Chip Disable to WAIT High-Z Output
CLK Rise or Fall Time
Clock to WAIT Valid
CLK HIGH or LOW Time
Setup Time to Activate CLK Edge
Burst WRITE Cycle Timing Requirements
Notes: 1. When configured for synchronous mode (BCR[15] = 0), a refresh opportunity must be pro-
2. Clock rates below 50 MHz (
vided every
tions: a) clocked CE# HIGH, or b) CE# HIGH for greater than 15ns.
64Mb: 4 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
t
CEM. A refresh opportunity is satisfied by either of the following two condi-
Symbol
t
t
t
t
t
t
t
t
t
t
t
CBPH
CEM
CEW
CLK
CSP
HD
HZ
KHKL
KHTL
KP
SP
t
36
CLK > 20ns) are allowed as long as
Min
12.5
4.5
5
1
2
4
3
-708
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Max
7.5
1.8
20
20
8
8
9
Min
15
5
1
5
2
5
3
-706/-856
Electrical Characteristics
Max
7.5
2.0
20
20
11
©2003 Micron Technology, Inc. All rights reserved.
t
8
8
CSP specifications are met.
Units
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
1
1
3
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