NP5Q128A13ESFC0E Micron Technology Inc, NP5Q128A13ESFC0E Datasheet
NP5Q128A13ESFC0E
Specifications of NP5Q128A13ESFC0E
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NP5Q128A13ESFC0E Summary of contents
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Quad/Dual/Single Serial Interface, 128-Kbyte Sectors Phase Change Memory (PCM) with 66MHz SPI Bus Interface Features SPI bus compatible serial interface Maximum Clock Frequency o – 66MHz ( – 33MHz (-30 to +85 C) 2.7 V ...
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Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Write disable (WRDI ...
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List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Description 1.1 Introduction Numonyx® Omneo™ Phase Change Memory for embedded applications offers all of the best attributes from other memory types in a new, highly scalable and flexible technology. Omneo™ P5Q PCM is a new type of nonvolatile semiconductor ...
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Product Description The Omneo™ P5Q PCM s a 128-Mbit ( SPI phase change memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. Omneo™ P5Q PCM product supports four new, high-performance dual and ...
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Figure 1. Logic diagram Table 1. Signal names Standard x1 Mode Signal Name Function C Serial Clock D Serial Data Input (DQ0) Q Serial Data Output (DQ1) S Chip Select W Write Protect (DQ2) HOLD Hold (DQ3 ...
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Figure 2. SO16 connections HOLD/DQ3 DQ1 don’t use. User must float these pins. 2. See Package mechanical section for package dimensions, and how to identify pin-1. 3. For SO8 package solutions please contact your local Numonyx field ...
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Signal descriptions 2.1 Serial data input (D/DQ0) This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock ...
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Hold (HOLD/DQ3) The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device. During the hold condition, the serial data output (DQ1) is high impedance, and serial data input (DQ0) and Serial ...
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SPI modes These devices can be driven by a microcontroller with its SPI peripheral running in either of the two following modes: – CPOL=0, CPHA=0 – CPOL=1, CPHA=1 For these two modes, input data is latched in on the ...
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SPI bus in high impedance. Example pF, that is R*C p master never leaves the SPI ...
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Operating features Note: Definition of ‘Program’, ‘Bit-alterable Write’ and ‘Program on All 1s’: – Program on Omneo™ P5Q PCM devices writes only 0s of the user data to the array and treats 1s as data masks. This is similar ...
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Sector erase and bulk erase A sector can be erased to all 1s (FFh time using the sector erase (SE) instruction. The entire memory can be erased using the bulk erase (BE) instruction. This starts an internal ...
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Protection modes There are protocol-related and specific hardware and software protection modes. They are described below. 4.8.1 Protocol-related protections The environments where non-volatile memory devices are used can be very noisy. No SPI device can operate correctly in the ...
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Table 2. Protected area sizes Status register contents bit bit 3 bit 2 bit 1 bit ...
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Hold condition The Hold (HOLD) signal is used to pause any serial communications with the device without resetting the clocking sequence. However, taking this signal Low does not terminate any write status register, program or erase cycle that is ...
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Memory organization The memory is organized as: – 16,772,216 bytes (8 bits each) – 8 Super Page programming regions (16 sectors each) – 128 sectors (128 Kbytes each) – 262,144 pages (64 bytes each) Each page can be individually ...
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Table 3. Memory organization (continued) Sector 77 9A0000 76 980000 75 960000 74 940000 73 920000 72 900000 71 8E0000 70 8C0000 69 8A0000 68 880000 67 860000 66 840000 65 820000 64 800000 63 7E0000 62 7C0000 61 7A0000 ...
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Table 3. Memory organization (continued) Sector Address range 7 0E0000 0FFFFF 6 0C0000 0DFFFF 5 0A0000 0BFFFF 4 080000 09FFFF Table 4. Organization of Super Page regions Programming Sectors Region 7 112 to 127 111 5 80 ...
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Instructions All instructions, addresses and data are shifted in and out of the device, most significant bit first. Serial data input DQ0 is sampled on the first rising edge of Serial Clock (C) after Chip Select (S) is driven ...
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Table 5. Instruction set Instruction Description WREN Write enable WRDI Write disable RDID Read identification RDSR Read status register WRSR Write status register READ Read data bytes FAST_READ Read data bytes at higher speed DOFR Dual output fast read QOFR ...
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Write enable (WREN) The write enable (WREN) instruction The write enable latch (WEL) bit must be set prior to every page program (PP), dual input fast program (DIFP), sector erase (SE), bulk erase (BE), write status register (WRSR) instruction. ...
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Write disable (WRDI) The write disable (WRDI) instruction The write disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the instruction code, and then driving Chip Select (S) High. The write enable latch (WEL) bit is ...
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Read identification (RDID) The read identification (RDID) instruction allows to read the device identification data: – Manufacturer identification (1 byte) – Device identification (2 bytes) The manufacturer identification is assigned by JEDEC, and has the value 20h for Numonyx. ...
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Read status register (RDSR) The read status register (RDSR) instruction allows the status register to be read. The status register may be read at any time, even while a program, erase, write status register cycle is in progress. When ...
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Top/bottom bit The top/bottom (TB) bit is non-volatile. It can be set and reset with the write status register (WRSR) instruction provided that the write enable (WREN) instruction has been issued. The top/bottom (TB) bit is used in conjunction ...
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Write status register (WRSR) The write status register (WRSR) instruction allows new values to be written to the status register. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable ...
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Table 8. Protection modes SRWD W bit defined by the values in the block protect (BP3, BP2, BP1, BP0) bits of the status register, as shown in Table 2. The ...
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If Write Protect (W) is permanently tied High, the hardware protected mode (HPM) can never be activated, and only the software protected mode (SPM), using the block protect (BP3, BP2, BP1, BP0) bits of the status register, can be used. ...
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Read data bytes at higher speed (FAST_READ) The device is first selected by driving Chip Select (S) Low. The instruction code for the read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte address A[23:0] and ...
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Dual output fast read (DOFR) The dual output fast read (DOFR) instruction is very similar to the read data bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on two pins (pin DQ0 and pin ...
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Quad output fast read (QOFR) The quad output fast read (QOFR) instruction is very similar to the read data bytes at higher speed (FAST_READ) instruction, except that the data are shifted out on four pins (pins DQ0, DQ1, DQ2 ...
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Page program (PP) Note: This definition applies to all flavors of Page Program: Legacy Program, Bit-alterable Write and Program on all 1s. The page program (PP) instruction allows bytes to be programmed/written in the memory. Before it can be ...
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Figure 15. Page program (PP) instruction sequence DQ0 Data byte DQ0 MSB 36/ ...
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Dual input fast program (DIFP) Note: This definition applies to all flavors of Dual input fast program: Legacy Program, Bit- alterable Write and Program on all 1s. The dual input fast program (DIFP) instruction is very similar to the ...
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Figure 16. Dual input fast program (DIFP) instruction sequence DQ0 DQ1 DQ0 DATA DQ1 MSB 38/ ...
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Quad input fast program (QIFP) Note: The following description applies to all flavors of Quad input fast program: Legacy Program, Bit-alterable Write and Program on all 1s. The quad input fast program (QIFP) instruction is very similar to the ...
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Figure 17. Quad input fast program (QIFP) instruction sequence DQ0 DQ0 DQ1 DQ1 DQ2 DQ2 DQ3 DQ3 1. Once 32h is recognized, W and HOLD functionality is automatically disabled. 40/56 32h 32h Don’t care Don’t ...
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Sector erase (SE) The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector. Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction ...
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Bulk erase (BE) The bulk erase (BE) instruction sets all bits to ‘1’ (FFh). Before it can be accepted, a write enable (WREN) instruction must previously have been executed. After the write enable (WREN) instruction has been decoded, the ...
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Power-up and power-down At power-up and power-down, the device must not be selected (that is Chip Select (S) must follow the voltage applied on V – V (min) at power-up, and then for a further delay ...
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Figure 20. Power-up timing (max (min) Reset state of the device V WI Table 9. Power-up timing and V Symbol ( (min Low VSL CC (1) t Time delay to ...
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Maximum ratings Stressing the device outside the ratings listed in cause permanent damage to the device. These are stress ratings only, and operation of the device at these, or any other conditions outside those indicated in the operating sections ...
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DC and AC parameters This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow are derived from tests performed under the ...
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Table 14. Capacitance Symbol Parameter C Input/output capacitance (DQ0/DQ1) IN/OUT C Input capacitance (other pins Sampled only, not 100% tested Test condition OUT =25 °C and ...
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Table 15. DC characteristics Symbol Parameter I Input leakage current LI I Output leakage current LO I Standby current CC1 Operating current (READ) I CC3 Operating current (DOFR) Operating current (QOFR) Operating current (PP) I Operating current (DIFP) CC4 Operating ...
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Table 16. AC characteristics Test conditions specified in Symbol Alt. Clock frequency for the following instructions: DOFR DIFP, FAST_READ, SE, BE, WREN, WRDI, RDID RDSR, WRSR (0 to +70 Clock frequency for the following instructions: QOFR, ...
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Table 16. AC characteristics Test conditions specified in Symbol Alt. t Write status register cycle time W Page program cycle time (64 bytes) (Legacy Program & Bit-alterable Write) ( Page program cycle time (64 bytes) (Program on all ...
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Figure 23. Write protect setup and hold timing during WRSR when SRWD=1 W tWHSL S C DQ0 High Impedance DQ1 Figure 24. Hold timing S C DQ1 DQ0 HOLD tHLCH tCHHL tCHHH tHLQZ tHHQX tSHWL AI07439c tHHCH AI13746 51/56 ...
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Figure 25. Output timing S C tCLQV tCLQX tCLQX DQ1 ADDR. DQ0 LSB IN 52/56 tCH tCLQV tCL tQLQH tQHQL tSHQZ LSB OUT AI13729 ...
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Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box ...
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... Ordering information This section defines all active line items that can be ordered. Table 18. Active Line Item Ordering Table Part Number NP5Q128A13ESFC0E NP5Q128AE3ESFC0E Note: For SO8 packaging solutions please contact your local Numonyx representative for details. 54/56 Description 3V, SOIC, PbFree,10.34x10.34x2.54, 16 lead (0 to +70 3V, SOIC, PbFree,10 ...
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Revision history Table 19. Document revision history Date Revision June 2009 August 2009 April 2010 July 2010 1 Initial release Removed Numonyx Confidential Added Figures 23&24 2 Revised Hold Condition Verbiage 4.9 Removed Streaming Mode from Datasheet Added P5Q ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE ...