KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 37

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.8.6
4.9
4.9.1
4.10
Intel
®
Table 4-2. Write Buffer Burst Operation for Read-Hit Operations
E8870DH DDR Memory Hub (DMH) Datasheet
Invalid and Unsupported DIMM Transactions
The DMH does not support or prevent cycle combinations where data interruption or early
termination (as defined in the Jedec Standard JESD79) would result. Further, the DMH does not
prevent or support any combinations of transactions that would create bus contention (i.e. where
two DIMMs would be required to drive data simultaneously onto a branch channel). Also, since the
DMH does not provide the Burst Stop DDR command, it does not provide a mechanism to
interrupt writes for reads. The DMH provides a precharge command, but does not support early
read or write termination due to precharge. Even though it is possible to create the conditions for
these events, they are invalid to the DMH.
Error Mechanisms
Support for Memory Device Failure
The error isolation and correction feature is achieved by mapping the DIMM data bits with respect
to the Main Channel as used by the SNC. An SNC that can correct a single bit in each transfer can
then correct any single device failure.
System Clocking
The DMH receives the 400 MHz differential RAC clock from the system’s Direct RAC Clock
Generator (DRCG) (refer to
from the 400 MHz RAC clock. From the 200 MHz core clock, the DMH generates eight pairs of
SCLK (SDRAM clocks) for the DDR DIMMs. There is a 1 MHz serial I/O clock input for the
MSIO bus, which is used to generate a 100 kHz serial I/O clock on the DDR DIMM side. The
1 MHz MSIO clock must be provided at all times.
Burst Length
16-Byte
32-Byte
Starting Address
Figure
(C2, C1, C0)
xx0
xx1
x00
x01
x10
x11
4-5). The core frequency of the DMH is 200 MHz, derived
0,1
Not Supported
0,1,2,3
Not Supported
2,3,0,1
Not Supported
Sequential Mode
Functional Description
4-9