KC82870DH S L5X2 Intel, KC82870DH S L5X2 Datasheet - Page 41

• Manufacturer Part Number: KC82870DH S L5X2
• Manufacturer: Intel

Specifications of KC82870DH S L5X2

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Not Compliant

4.11.4.1
Intel
®
Figure 4-10. Connection of DIMM Serial I/O Signals
E8870DH DDR Memory Hub (DMH) Datasheet
BSIO Asynchronous Handshake
The I
command (MSIO SPDW or SPDR), software is responsible for verifying command completion
before another SPD command can be issued. Software can determine the status of an SPD
command by observing the SPD register.
An SPD command has completed when any one command completion field (RDO, WOD, BBE) of
the SPD register (see
to 1. An SPDR command has successfully completed when the RDO field is observed set to 1. An
SPDW command has successfully completed when the WOD field is observed set to 1. An
unsuccessful command termination causes the BBE field to be set to 1. The DMH will clear the
SPD register command completion fields automatically whenever an SPDR or SPDW command is
initiated. An application may begin polling the register immediately after initiating an SPD
command.
Software can determine when an SPD command is being performed by observing the BUSY field
of the SPD register. When this bit is observed set to 1, the interface is busy performing a command.
The Register Read MSIO transaction initiates the SPDR operation and will not directly receive the
SPD data in its SD packet field. The SPDR operation must be tunneled across the much slower
BSIO interface, and will not return data on time for transfer to the SD packet field of the initiating
Register Read MSIO transaction. Instead, valid SPD data is stored in the DATA field of the SPD
register upon successful completion of the SPDR operation (indicated by 1 in the RDO field of the
SPD register).
Unsuccessful command termination can be caused by one of two conditions. The first condition
occurs when an EEPROM does not acknowledge a packet at any of the required ACK points. The
second condition occurs when an EEPROM throttles the serial clock for more than 25 ms. These
conditions generate the same end result (BBE field set to 1).
2
C interface is a non-deterministic, asynchronous interface. Once software issues an SPD
Section 3.10, “SPD – Serial Presence Detect Status Register”)
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
DIMM
DIMM
DIMM
DIMM
SCL/
SDA
DMH
DIMM
DIMM
DIMM
DIMM
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
SA0
SA1
SA2
Functional Description
is observed set
001189a
4-13