M395T5750EZ4CE65 Samsung Semiconductor, M395T5750EZ4CE65 Datasheet - Page 23

• Manufacturer Part Number: M395T5750EZ4CE65
• Manufacturer: Samsung Semiconductor

Specifications of M395T5750EZ4CE65

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 240FBDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 512Mb
• Package Type: FBDIMM
• Maximum Clock Rate: 667MHz
• Operating Supply Voltage (typ): 1.8V
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Table 11 : V
Table 12 : Reference Clock Input Specifications
Note :
1.133MHz for PC2-4200, 166MHz for PC2-5300 and 200MHz for PC2-6400.
2. Measured with SSC disabled.
3. Measured differentially through the range of 0.175V to 0.525V.
4. The crossing point must meet the absolute and relative crossing point specification simultaneously.
5. V
6. Measured with a single-ended input voltage of 1V.
7. Applies to reference clocks SCK and SCK.
8. Difference between SCK and SCK input.
9. T1 = [Tdatapath-Tclockpath](excluding PLL loop delays). This parameter is not a direct clock output parameter but in indirectly determines the clock
10. The net transport delay is the difference in time of flight between associated data and clock paths. The data path is defined from the reference clock
11. Direct measurement of phase jitter records over 1016 periods is impractical. It is expected that the jitter will be measured over a smaller, yet statistically
12. Measured with SSC enabled on reference clock generator.
13. As measured after the phase jitter filter. This number is separate from the receiver jitter budget that is defined by the TRXTotal - MIN parameters.
FBDIMM
Idle current, DDR2 SDRAM device power down
Active power, 50% DDR2 SDRAM BW
Reference clock frequency @3.2 Gb/s
(nominal 133.33 MHz)
Reference clock frequency @4.0 Gb/s
(nominal 166.67 MHz)
Reference clock frequency @4.8 Gb/s
(nominal 200 MHz)
Rise time, fall time
Voltage high
Voltage low
Absolute crossing point
Relative crossing
Percent mismatch between rise and fall
times
Duty cycle of reference clock
Clock leakage current
Clock input capacitance
Clock input capacitance delta
Transport delay
Phase jitter sample size
Reference clock jitter, filtered
where Vhavg is the average of V
output parameter T
source, through the TX, to data arrival at the data dampling point in the RX. The clock path is defined from the reference clock source to clock arrival
at the same sampling point. The path delays are caused by copper trace routes. on-chip routing, on-chip buffering, etc. They include the time-of flight
of interpolators or other clock adjustment mechanisms. They do not include the phase delays caused by finite PLL loop bandwidth because these de-
lays are modeled by the PLL transfer functions.
significant, sample size and the total jitter at 10
CROSS_REL_(MIN)
TT
Parameter
Currents
and V
REF-JITTER.
CROSS_REL(MAX)
SCK-HIGHM.
Description
are derived using the following calculation : Min = 0.5(V
T
T
SCK-RISE-FALL-MATCH
SCK-RISE
T
16
SCK-DUTYCYCLE
V
V
T
samples extrapolated from an estimate of the sigma of the random jitter components.
fRefclk-3.2
fRefclk-4.0
fRefclk-4.8
NSAMPLE
V
V
CROSS-ABS
CROSS-REL
REF-JITTER
C
Symbol
SCK-HIGH
SCK-LOW
C
I_CK(D)
I
I-CK
T1
I-CK
, T
SCK-FALL
23 of 33
calculated
126.67
158.33
190.00
-0.25
-150
10
MIN
175
660
250
-10
0.5
40
-
16
Values
calculated
Symbol
133.40
166.75
200.10
havg
MAX
ITT1
ITT2
0.25
700
850
550
10
60
10
40
2
5
-0.710)+0.250;and Max=0.5(V
Rev. 1.51 January 2008
Periods
Units
Typ
500
500
MHz
MHz
MHz
mV
mV
mV
uA
pF
pF
ps
ns
ps
%
%
DDR2 SDRAM
MAX
700
700
havg
-0.710)+0.550,
12,13
Note
9, 10
1.2
1.2
1.2
4,5
6,7
11
3
4
7
8
Units
mA
mA