MT36LSDF12872Y-13ED1 Micron Technology Inc, MT36LSDF12872Y-13ED1 Datasheet
MT36LSDF12872Y-13ED1
Specifications of MT36LSDF12872Y-13ED1
Related parts for MT36LSDF12872Y-13ED1
MT36LSDF12872Y-13ED1 Summary of contents
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... MT36LSDF6472 – 512MB MT36LSDF12872 – 1GB For the latest data sheet, refer to Micron’s Web site: Features • 168-pin, dual in-line memory module (DIMM) • PC133-compliant • Registered inputs with one-clock delay • Phase-lock loop (PLL) clock driver to reduce loading • Utilizes 133 MHz SDRAM components • ...
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... Part Number MT36LSDF6472G-133__ MT36LSDF6472Y-133__ MT36LSDF12872G-13E__ MT36LSDF12872Y-13E__ MT36LSDF12872G-133__ MT36LSDF12872Y-133__ Note: The designators for component and PCB revision are the last two characters of each part number. Consult factory for current revision codes. Example: MT36LSDF12872G-133D1. PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G.fm - Rev. E 10/05 EN 512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM ...
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Pin Assignments and Descriptions Table 4: Pin Assignment 168-Pin DIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol CB1 DQ0 ...
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... BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. SCL Input Serial clock for presence-detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect address inputs: These pins are used to configure the presence-detect device. REGE Input Register enable: REGE permits the DIMM to operate in “ ...
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... Functional Block Diagram Per industry standard, Micron modules utilize various component speed grades, as ref- erenced in the module part number guide at Standard modules use the following SDRAM devices: MT48LC32M4A2FB (512MB); MT48LC64M4A2FB (1GB). Lead-free modules use the following SDRAM devices: MT48LC32M4A2BB (512MB) ...
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Figure 3: Functional Block Diagram RS0# RS1# RS2# RS3# CKE0 A0–A11 (512MB) A0–A12 (1GB) DQMB0–DQMB7 10K V DD REGE PLL CLK Note: All resistor values are 10Ω unless otherwise specified. PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G.fm - Rev. E 10/05 EN 512MB, ...
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... READ or WRITE command are used to select the starting column location for the burst access. SDRAM modules provide for programmable read or write locations, or full page, with a burst terminate option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. ...
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... DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Initialization SDRAMs must be powered up and initialized in a predefined manner. Operational pro- cedures other than those specified may result in undefined operation ...
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... Module Address Bus A8 A6 A11 A10 Reserved WB Op Mode CAS Latency Program M11, M10 = “0, 0, 0” to ensure compatibility with future devices. 1GB Module Address Bus A12 A11 A8 A6 A10 Reserved WB Op Mode CAS Latency Program M12, M11, M10 = “0, 0, 0” ...
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Table 6: Burst Definition Table Full page (y) Notes: 1. For full-page accesses 2,048. 2. For A0–A9, A11 will select the block of two burst; A0 selects the starting column within the block. 3. For ...
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Figure 5: CAS Latency Diagram CLK COMMAND DQ CLK COMMAND DQ Burst Type Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit ...
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Write Burst Mode When programmed via M0–M2 applies to both READ and WRITE bursts; when the programmed BL applies to READ bursts, but write accesses are single- location (nonburst) accesses. Table 7: CAS ...
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Electrical Specifications Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of ...
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... Auto refresh current CS# = HIGH; CKE = HIGH Self refresh current: CKE ≤ 0.2V Note Value calculated as one module rank in this operating condition, and all other module ranks in power-down ( Value calculated reflects all module ranks in this operating condition. Table 13: Capacitance Note: 2 ...
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Table 14: SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions Notes 11, 32; notes appear on pages 17 and 18 AC Characteristics Parameter Access time from CLK (positive edge) Address hold time Address setup time ...
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Table 15: AC Functional Characteristics Notes 11; notes appear on pages 17 and 18 Parameter READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit ...
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Notes 1. All voltages referenced This parameter is sampled. V test biased at 1.4V with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are ...
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... Refer to device data sheet for timing waveforms. 32. The value for 33. This AC timing function will show an extra clock cycle when in registered mode. 34. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G ...
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PLL and Register Specifications Table 16: Register Timing Requirements and Switching Characteristics Register Symbol f clock t Propagation delay, Single rank pd1 SSTL t Propagation delay, Dual rank pd2 bit pattern by JESD82 Table ...
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... The system used for experimental purposes is a dual-processor 600 MHz work station, fully loaded with four MT36LSDT12872G modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. 3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from its case and mounted in a Eiffel-type low air speed wind tun- nel ...
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Serial Presence-Detect SPD Clock and Data Conventions Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, and Figure ...
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Figure 8: Definition of Start and Stop SCL SDA Figure 9: Acknowledge Response From Receiver SCL from Master Data Output from Transmitter Data Output from Receiver Table 18: EEPROM Device Select Code The most significant bit (b7) is sent first ...
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Figure 10: SPD EEPROM Timing Diagram SCL t SU:STA SDA IN SDA OUT PDF: 09005aef807da15c/Source: 09005aef80f69382 SDF36C64_128x72G.fm - Rev. E 10/05 EN 512MB, 1GB (x72, ECC, DR): 168-Pin SDRAM RDIMM HIGH LOW t HD:STA ...
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Table 20: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to V Parameter/Condition Supply voltage Input high voltage: Logic 1; All inputs Input low voltage: Logic 0; All inputs Output low voltage 3mA OUT Input leakage current: ...
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... Byte Description 0 Number of bytes used by Micron 1 Total number of SPD memory bytes 2 Memory type 3 Number of row addresses 4 Number of column addresses 5 Number of module ranks 6 Module data width 7 Module data width (continued) 8 Module voltage interface levels t 9 SDRAM cycle time SDRAM access from CLK, ...
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... ECC, DR): 168-Pin SDRAM RDIMM = +3.3V ±0.3V DD Entry (Version 66ns (-13E) 71ns (-133) REV. 2.0 -13E -133 MICRON 1–9 1–11 0 100/133 MHz t RAS used for the -13E module is calculated from Micron Technology, Inc., reserves the right to change products or specifications without notice. 26 Serial Presence-Detect MT36LSDF6472 MT36LSDF12872 ...
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... U26 U25 U24 U23 U22 U34 U33 U32 U40 1.661 (42.18) ® Micron Technology, Inc., reserves the right to change products or specifications without notice. 27 Module Dimensions MAX or typical where noted. MIN U8 U9 U10 1.705 (43.31) 1.695 (43.05) U16 U17 U18 0.700 (17.78) ...