MT9KSF12872PY-1G1D1 Micron Technology Inc, MT9KSF12872PY-1G1D1 Datasheet
MT9KSF12872PY-1G1D1
Specifications of MT9KSF12872PY-1G1D1
Related parts for MT9KSF12872PY-1G1D1
MT9KSF12872PY-1G1D1 Summary of contents
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... DDR3 SDRAM RDIMM MT9KSF12872PY – 1GB For component data sheets, refer to Micron’s Web site: Features • Low voltage DDR3 functionality and operations supported as defined in the component data sheet • 1.35V 0.0675V ± DD • Backward-compatible with standard 1.5V DDR3 systems • ...
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... Data sheets for the base device parts can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT9KSF12872PY-1G1A1. PDF: 09005aef833a64f8/Source: 09005aef833a64ce KSF9C128x72PY.fm - Rev. A 4/08 EN 1GB (x72, ECC, SR, 1 ...
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Pin Assignments and Descriptions Table 4: Pin Assignments 240-Pin RDIMM Front Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol DQ25 61 REF ...
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... I/O Serial data: SDA is a bidirectional pin used to transfer addresses and data into and out of the SPD EEPROM on the module. EVENT# Output Temperature event: The optional EVENT# pin is used to flag critical module temperatures when used in conjunction with a temperature senor Output Parity error output: Parity error found on the command, address, and control bus. ...
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... REF V CA Supply Reference voltage: Command, address, and control (V REF NC – No connect: These pins are not connected on the module. PDF: 09005aef833a64f8/Source: 09005aef833a64ce KSF9C128x72PY.fm - Rev. A 4/08 EN 1GB (x72, ECC, SR, 1.35V) 240-Pin DDR3 SDRAM RDIMM Pin Assignments and Descriptions Description /2). DD Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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Functional Block Diagram Figure 2: Functional Block Diagram RS0# DQS0 DQS0# DM0/DQS9 DQS9# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 V SS DQS1 DQS1# DM1/DQS10 DQS10# DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 V SS DQS2 DQS2# DM2/DQS11 ...
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... The double data rate architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corre- sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins ...
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... Platform Memory Module Thermal Sensor Component Specification.” Serial Presence-Detect EEPROM Operation 1.35V DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC Standard JC-45 “Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules.” ...
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... Back view U10 U11 5.0 (0.197) TYP 71 (2.79) 47 (1.85) TYP TYP tive owners. Micron Technology, Inc., reserves the right to change products or specifications without notice. 9 Module Dimensions U6 30.5 (1.2) 29.85 (1.175) 17.3 (0.68) TYP 9.5 (0.374) TYP TYP Pin 120 U12 3 (0.118) x4 TYP Pin 121 © ...