MT18HVS25672PKY-53EE1 Micron Technology Inc, MT18HVS25672PKY-53EE1 Datasheet - Page 4

• Manufacturer Part Number: MT18HVS25672PKY-53EE1
• Manufacturer: Micron Technology Inc

Specifications of MT18HVS25672PKY-53EE1

• Main Category: DRAM Module
• Sub-category: DDR2 SDRAM
• Module Type: 244VLP MiniRDIMM
• Device Core Size: 72b
• Organization: 256Mx72
• Total Density: 2GByte
• Chip Density: 1Gb
• Access Time (max): 50ps
• Maximum Clock Rate: 533MHz
• Operating Supply Voltage (typ): 1.8V
• Operating Current: 1.233A
• Number Of Elements: 18
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 244
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Figure 2:
PDF: 09005aef8281e0a3/Source: 09005aef8281d7ea
HVS18C256_512x72PK.fm - Rev. A 8/07 EN
RAS#, CAS#, WE#
(RDQS0–RDQS8)
DQS0#–DQS8#
CKE0, CKE1#
ODT0, ODT1
DQS0–DQS8,
DQ0–DQ63
DM0–DM8
CK0, CK0#
BA0–BA2
SA0–SA2
CB0–CB7
Symbol
.
S0#, S1#
E
A0–A15
RESET#
P
RR
SDA
AR
SCL
_O
_I
N
UT
Pin Descriptions
(open drain)
(LVCMOS)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
(SSTL_18)
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one
location out of the memory array in the respective bank. A10 sampled during a
PRECHARGE command determines whether the PRECHARGE applies to one device
bank (A10 LOW, device bank selected by BA0–BA1/BA2) or all device banks (A10
HIGH). The address inputs also provide the op-code during a LM command.
A0–A13 (2GB) and A0–A14 (4GB). A0–A15 are connected for parity.
Bank address inputs: BA0–BA1/BA2 define to which device bank an ACTIVE, READ,
WRITE, or PRECHARGE command is being applied. BA0–BA1/BA2 define which mode
register, including MR, EMR, EMR(2), and EMR(3), is loaded during the LOAD MODE
command.
Clock: CK and CK# are differential clock inputs. All address and control input signals
are sampled on the crossing of the positive edge of CK and the negative edge of CK#.
Output data (DQs and DQS/DQS#) is referenced to the crossings of CK and CK#.
Clock enable: CKE (registered HIGH) activates and CKE (registered LOW) deactivates
clocking circuitry on the DDR2 SDRAM.
On-die termination: ODT (registered HIGH) enables termination resistance internal
to the DDR2 SDRAM. When enabled ODT is only applied to each of the following pins:
DQ, DQS, DQS#, RDQS, RDQS#, CB, and DM. The ODT input will be ignored if disabled
via the LOAD MODE (LM) command.
Parity bit for the address and control bus. The non-parity version is not used.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Asynchronously forces all registered outputs LOW when RESET# is LOW. This signal can
be used during power up to ensure that CKE is LOW and DQs are High-Z.
Chip select: S# enables (registered LOW) and disables (registered HIGH) the command
decoder. All commands are masked when S# is registered HIGH. S# provides for
external rank selection on systems with multiple ranks. S# is considered part of the
command code.
Presence-detect address inputs: These pins are used to configure the presence-
detect device.
Serial clock for presence-detect: SCL is used to synchronize the presence-detect
data transfer to and from the module.
Check bits.
Data input mask: DM is an input mask signal for write data. Input data is masked
when DM is sampled HIGH along with that input data during a WRITE access. DM is
sampled on both edges of DQS. Although DM pins are input-only, the DM loading is
designed to match that of DQ and DQS pins. If RDQS is enabled, RDQS0#–RDQS8# are
used only during the READ command. If RDQS is disabled, RDQS0–RDQS8 become
DM0–DM8 and RDQS0#–RDQS8 are not used.
Data input/output: Bidirectional data bus.
Data strobe: Output with read data, input with write data for source synchronous
operation. Edge-aligned with read data, center-aligned with write data. DQS# is only
used when differential data strobe mode is enabled via the LM command.
Serial presence-detect data: SDA is a bidirectional pin used to transfer addresses
and data into and out of the presence-detect portion of the module.
Parity error found on the address and control bus. The non-parity version is not used.
2GB, 4GB (x72, DR) 244-Pin DDR2 VLP Mini-RDIMM
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
©2007 Micron Technology, Inc. All rights reserved.