MT9JSF12872PY-1G1D1 Micron Technology Inc, MT9JSF12872PY-1G1D1 Datasheet - Page 7

• Manufacturer Part Number: MT9JSF12872PY-1G1D1
• Manufacturer: Micron Technology Inc

Specifications of MT9JSF12872PY-1G1D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 128Mx72
• Total Density: 1GByte
• Chip Density: 1Gb
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 1.98A
• Number Of Elements: 9
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

General Description
Fly-By Topology
Registering Clock Driver Operation
Parity Operations
PDF: 09005aef829eedac
Rev. B 06/09
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory mod-
ules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM mod-
ules use DDR architecture to achieve high-speed operation. DDR3 architecture is
essentially an 8n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM
module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data trans-
fers at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, com-
mand, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write-leveling feature of DDR3.
Registered DDR3 SDRAM modules use a registering clock driver device consisting of a
register and a phase-lock loop (PLL). The device complies with the JEDEC standard
“Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Se-
lects for DDR3 RDIMM Applications.”
The register section of the registering clock driver latches command and address input
signals on the rising clock edge. The PLL section of the registering clock driver receives
and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The
register(s) and PLL reduce clock, control, command, and address signals loading by iso-
lating DRAM from the system controller.
The registering clock driver can accept a parity bit from the system’s memory control-
ler, providing even parity for the control, command, and address bus. Parity errors are
flagged on the Err_Out# pin. Systems not using parity are expected to function without
issue if Par_In and Err_Out# are left as no connects to the system.
1GB (x72, ECC, SR) 240-Pin DDR3 SDRAM RDIMM
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
General Description
©2007 Micron Technology, Inc. All rights reserved.