MT36JSZF51272PY-1G1D1 Micron Technology Inc, MT36JSZF51272PY-1G1D1 Datasheet - Page 4

• Manufacturer Part Number: MT36JSZF51272PY-1G1D1
• Manufacturer: Micron Technology Inc

Specifications of MT36JSZF51272PY-1G1D1

• Main Category: DRAM Module
• Sub-category: DDR3 SDRAM
• Module Type: 240RDIMM
• Device Core Size: 72b
• Organization: 512Mx72
• Total Density: 4GByte
• Chip Density: 1Gb
• Maximum Clock Rate: 1.066GHz
• Operating Supply Voltage (typ): 1.5V
• Operating Current: 3.06A
• Number Of Elements: 36
• Operating Supply Voltage (max): 1.575V
• Operating Supply Voltage (min): 1.425V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Pin Count: 240
• Mounting: Socket
• Lead Free Status / RoHS Status: Compliant

Table 5: Pin Descriptions
PDF: 09005aef830b8963
JSZF36C512x72P.pdf – Rev. B 7/09 EN
RAS#, CAS#,
DQS#[17:0]
CK0, CK0#
DQS[17:0]
ODT[1:0]
DQ[63:0]
Err_Out#
Symbol
CKE[1:0]
A[15:0]
BA[2:0]
RESET#
SA[2:0]
CB[7:0]
S#[1:0]
Par_In
WE#
SDA
SCL
(open drain)
(LVCMOS)
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
I/O
I/O
I/O
I/O
Description
Address inputs: Provide the row address for ACTIVATE commands, and the column
address and auto precharge bit (A10) for READ/WRITE commands, to select one loca-
tion out of the memory array in the respective bank. A10 is sampled during a
PRECHARGE command to determine whether the PRECHARGE applies to one bank
(A10 LOW, bank selected by BA[2:0]) or all banks (A10 HIGH). If only one bank is to
be precharged, the bank is selected by BA. A12 is also used for BC4/BL8 identification
as “BL on-the-fly” during CAS commands. The address inputs also provide the op-
code during the mode register command set. A[13:0] address the 1Gb DDR3 devices.
A[15:14] are needed to calculate parity on the command/address bus. A15 is needed
to calculate parity on the command/address bus.
Bank address inputs: BA[2:0] define the device bank to which an ACTIVATE, READ,
WRITE, or PRECHARGE command is being applied. BA[2:0] define which mode regis-
ter (MR0, MR1, MR2, and MR3) is loaded during the LOAD MODE command. BA[1:0]
are used as part of the parity calculation.
Clock: CK and CK# are differential clock inputs. All control, command, and address
input signals are sampled on the crossing of the positive edge of CK and the nega-
tive edge of CK#.
Clock enable: CKE enables (registered HIGH) and disables (registered LOW) internal
circuitry and clocks on the DRAM.
On-die termination: ODT (registered HIGH) enables termination resistance internal
to the DDR3 SDRAM. When enabled, ODT is only applied to the following pins: DQ,
DQS, DQS#, and DM. The ODT input will be ignored if disabled via the LOAD MODE
command.
Parity input: Parity bit for the address, RAS#, CAS#, and WE#.
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
Reset: An active LOW CMOS input referenced to V
CMOS input defined as a rail-to-rail signal with a DC HIGH ≥ 0.8 × V
0.2 × V
Chip select: S# enables (registered LOW) and disables (registered HIGH) the com-
mand decoder.
Presence-detect address inputs: These pins are used to configure the temperature
sensor/SPD EEPROM address range on the I
Serial clock for presence-detect: SCL is used to synchronize communication to and
from the temperature sensor/SPD EEPROM.
Check bits: Data used for ECC.
Data input/output: Bidirectional data bus.
Data strobe: DQS and DQS# are differential data strobes. Output with read data.
Edge-aligned with read data. Input with write data. Center-aligned with write data.
Serial data: SDA is a bidirectional pin used to transfer addresses and data into and
out of the temperature sensor/SPD EEPROM on the module on the I
Parity error output: Parity error found on the command and address bus.
DD
.
4GB (x72, ECC, DR) 240-Pin DDR3 SDRAM RDIMM
4
Micron Technology, Inc. reserves the right to change products or specifications without notice.
Pin Assignments and Descriptions
2
C bus.
SS
. The RESET# input receiver is a
©2008 Micron Technology, Inc. All rights reserved.
DD
2
C bus.
and DC LOW ≤