FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 120

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

CR0
This register can only be accessed when the
FDC is in the Configuration Mode and after the
CSR has been initialized to 00H. The default
BIT NO.
5,6
0
1
2
3
4
7
IDE ENABLE
IDE AT/XT
RESR
FDC POWER
FDC ENABLE
OSC
VALID
BIT NAME
A high level on this bit, enables the IDE (Default). A low level on
this bit disables the IDE.
A high level on this bit sets the IDE to AT type (Default). A low
level on this bit sets the IDE to XT type.
(This bit is Reserved - set to '0').
A high level on this bit, supplies power to the FDC (Default). A
low level on this bit puts the FDC in low power mode.
A high level on this bit, enables the FDC (Default for
FDC37C665GT).
(Default for FDC37C665GT).
6 5
0 0 Osc ON, Baud Rate Generator (BRG) Clock Enabled.
0 1 Osc is On, BRG Clock is ON when PWRGD is active. When
PWRGD is inactive, Osc is off and BRG Clock is Disabled
(Default).
1 0 (same as 0 1 case)
1 1 Osc OFF, BR Generator Clock Disabled
A high level on this software controlled bit indicates that a valid
configuration cycle has occurred. The control software must take
care to set this bit at the appropriate times. Set to zero after
power up.
Table 47 - CR0
120
value of this register after power up is 3BH for
the
FDC37C666GT.
A low level on this bit disables the FDC
FDC37C665GT
DESCRIPTION
and
2BH
for
the