FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 79

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

The following section describes the operation of
the registers.
RECEIVE BUFFER REGISTER (RB)
Address Offset = 0H, DLAB = 0, READ ONLY
This register holds the received incoming data
byte. Bit 0 is the least significant bit, which is
transmitted and received first. Received data is
double buffered; this uses an additional shift
register to receive the serial data stream and
convert it to a parallel 8 bit word which is
transferred to the Receive Buffer register. The
shift register is not accessible.
TRANSMIT BUFFER REGISTER (TB)
Address Offset = 0H, DLAB = 0, WRITE ONLY
This register contains the data byte to be
transmitted.
buffered, utilizing an additional shift register (not
accessible) to convert the 8 bit data word to a
serial format. This shift register is loaded from
the Transmit Buffer when the transmission of
the previous byte is complete.
INTERRUPT ENABLE REGISTER (IER)
Address Offset = 1H, DLAB = 0, READ/WRITE
The lower four bits of this register control the
enables of the five interrupt sources of the Serial
Port interrupt. It is possible to totally disable the
interrupt system by resetting bits 0 through 3 of
this register. Similarly, setting the appropriate
bits of this register to a high, selected interrupts
can be enabled. Disabling the interrupt system
inhibits the Interrupt Identification Register and
disables any Serial Port interrupt out of the
FDC37C665. All other system functions operate
in their normal manner, including the Line
Status and MODEM Status Registers.
contents of the Interrupt Enable Register are
described below.
Bit 0
This bit enables the Received Data Available
Interrupt (and timeout interrupts in the FIFO
mode) when set to logic "1".
The transmit buffer is double
The
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Bit 1
This bit enables the Transmitter Holding
Register Empty Interrupt when set to logic "1".
Bit 2
This bit enables the Received Line Status
Interrupt when set to logic "1".
sources causing the interrupt are Overrun,
Parity, Framing and Break.
Register must be read to determine the source.
Bit 3
This bit enables the MODEM Status Interrupt
when set to logic "1". This is caused when one
of the Modem Status Register bits changes
state.
Bits 4 through 7
These bits are always logic "0".
FIFO CONTROL REGISTER (FCR)
Address Offset = 2H, DLAB = X, WRITE
This is a write only register at the same location
as the IIR. This register is used to enable and
clear the FIFO's, set the RCVR FIFO trigger
level. Note: DMA is not supported.
Bit 0
Setting this bit to a logic "1" enables both the
XMIT and RCVR FIFO's.
logic "0" disables both the XMIT and RCVR
FIFO's and clears all bytes from both FIFO's.
When changing from FIFO Mode to non-FIFO
(16450) mode, data is automatically cleared
from the FIFO's. This bit must be a 1 when
other bits in this register are written to or they
will not be properly programmed.
Bit 1
Setting this bit to a logic "1" clears all bytes in
the RCVR FIFO and resets its counter logic to 0.
clearing.
The shift register is not cleared. This bit is self-
Clearing this bit to a
The Line Status
The error