FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 5

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

PIN NO.
48-51
53-56
28-34
41-43
44
45
46
52
36
35
Data Bus 0-7
nI/O Read
nI/O Write
Address Enable
I/O Address
FDC DMA
Request
nDMA Acknowle-
dge
Terminal Count
NAME
DESCRIPTION OF PIN FUNCTIONS
D0-D7
nIOR
nIOW
AEN
A0-A9
FDRQ
nDACK
TC
SYMBOL
HOST PROCESSOR INTERFACE
BUFFER
TYPE
I/O24
O24
I
I
I
I
I
I
5
The data bus connection used by the host
microprocessor to transmit data to and from
the FDC37C665GT.
high-impedance state when not in the output
mode.
This active low signal is issued by the host
microprocessor to indicate a read operation.
This active low signal is issued by the host
microprocessor to indicate a write operation.
Active high Address Enable indicates DMA
operations on the host data bus.
internally to qualify appropriate address
decodes.
These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles.
internally by the leading edge of nIOR and
nIOW.
This active high output is the DMA request
for byte transfers of data to the host. This
signal is cleared on the last byte of the data
transfer by the nDACK signal going low (or
by nIOR going low if nDACK was already
low as in demand mode).
An active low input acknowledging the
request for a DMA transfer of data. This
input enables the DMA read or write
internally.
This signal indicates to the FDC37C665GT
that data transfer is complete. TC is only
accepted when nDACK or nPDACK is low.
In AT and PS/2 model 30 modes, TC is
active high and in PS/2 mode, TC is active
low.
DESCRIPTION
These bits are latched
These pins are in a
Used