FDC37C665GT-MS Standard Microsystems (SMSC), FDC37C665GT-MS Datasheet - Page 87

• Manufacturer Part Number: FDC37C665GT-MS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C665GT-MS

• Pin Count: 100
• Lead Free Status / RoHS Status: Compliant

In this mode, the user's program will check
RCVR and XMITTER status via the LSR. LSR
definitions for the FIFO Polled Mode are as
follows:
*Note: The percentage error for all baud rates, except where indicated otherwise, is 0.2%.
Bit 0=1 as long as there is one byte in the
RCVR FIFO.
Bits 1 to 4 specify which error(s) have
occurred. Character error status is handled
the same way as when in the interrupt
DESIRED BAUD
115200
RATE
19200
38400
57600
134.5
1200
1800
2000
2400
3600
4800
7200
9600
110
150
300
600
50
75
Table 36 - Baud Rates Using 1.8462 MHz Clock (24 MHz/13)
GENERATE 16X CLOCK
DIVISOR USED TO
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
87
There is no trigger level reached or timeout
condition indicated in the FIFO Polled Mode,
however, the RCVR and XMIT FIFO's are still
fully capable of holding characters.
mode, the IIR is not affected since EIR bit
2=0.
Bit 5 indicates when the XMIT FIFO is
empty.
Bit 6 indicates that both the XMIT FIFO and
shift register are empty.
Bit 7 indicates whether there are any errors
in the RCVR FIFO.
BETWEEN DESIRED AND ACTUAL*
PERCENT ERROR DIFFERENCE
0.001
0.004
0.005
0.030
0.16
0.16
-
-
-
-
-
-
-
-
-
-
-
-
-