FW82801BA S L5WK Intel, FW82801BA S L5WK Datasheet - Page 296

• Manufacturer Part Number: FW82801BA S L5WK
• Manufacturer: Intel

Specifications of FW82801BA S L5WK

• Lead Free Status / RoHS Status: Not Compliant

LAN Controller Registers (B1:D8:F0)
7.2.10
296
PMDR—Power Management Driver Register
(LAN Controller—B1:D8:F0)
Offset Address:
Default Value:
The ICH5’s internal LAN controller provides an indication in the PMDR that a wake-up event has
occurred.
Bit
4:3
7
6
5
2
1
0
Link Status Change Indication — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = The link status change bit is set following a change in link status.
Magic Packet — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when a Magic Packet is received regardless of the Magic Packet wake-up disable
Interesting Packet — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set when an “interesting” packet is received. Interesting packets are defined by the
Reserved
ASF Enabled — RO. This bit is set to 1 when the LAN controller is in ASF mode.
TCO Request — R/WC.
0 = Software clears this bit by writing a 1 to it.
1 = This bit is set to 1b when the LAN controller is busy with TCO activity.
PME Status — R/WC. This bit is a reflection of the PME Status bit in the Power Management
Control/Status Register (PMCSR).
0 = Software clears this bit by writing a 1 to it.This also clears the PME Status bit in the PMCSR and
1 = Set upon a wake-up event, independent of the PME Enable bit.
bit in the configuration command and the PME Enable bit in the power management CSR.
LAN controller packet filters.
deasserts the PME signal.
1Bh
00h
Intel
Description
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC
8 bits