FW82801BA S L5WK Intel, FW82801BA S L5WK Datasheet - Page 304
FW82801BA S L5WK
Manufacturer Part Number
FW82801BA S L5WK
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5WK.pdf
(671 pages)
Specifications of FW82801BA S L5WK
Lead Free Status / RoHS Status
Not Compliant
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Hub Interface to PCI Bridge Registers (D30:F0)
8.1.4
304
Note: For the writable bits, software must write a 1 to clear bits that are set. Writing a 0 to the bit has no
PCISTS—PCI Status Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
effect.
10:9
Bit
4:0
15
14
13
12
11
8
7
6
5
Detected Parity Error (DPE) — R/WC.
0 = Parity error not detected.
1 = Indicates that the Intel
Signaled System Error (SSE)
0 = Error described below not detected.
1 = An address, or command parity error, or special cycles data parity error has been detected on
Received Master Abort (RMA) — R/WC.
0 = Master abort not received from hub interface.
1 = ICH5 received a master abort from the hub interface device.
Received Target Abort (RTA) — R/WC.
0 = Target abort not received from hub interface.
1 = ICH5 received a target abort from the hub interface device. The TCO logic can cause an SMI#,
Signaled Target Abort (STA) — R/WC.
0 = ICH5 did not signal a target abort on hub interface.
1 = ICH5 signals a target abort condition on the hub interface.
DEVSEL# Timing Status (DEV_STS) — RO.
00h = Fast timing. This register applies to the hub interface; therefore, this field does not matter.
Master Data Parity Error Detected (MDPD) — R/WC. Since this register applies to the hub
interface, the ICH5 must interpret this bit differently than it is in the PCI Local Bus Specification,
Revision 2.3.
0 = Parity error not detected on hub interface.
1 = ICH5 detects a parity error on the hub interface and the Parity Error Response bit in the PCI
Fast Back to Back Capable (FB2BC) — RO. Hardwired to 1.
Reserved
66 MHz Capable (66MHZ_CAP) — RO. Hardwired to 0.
Reserved
HP_Unsupported bit (D30:F0:40h bit 20) is 0. This bit gets set even if the Parity Error Response
bit (D30:F0:04 bit 6) is not set.
the PCI bus, and the Parity Error Response bit (D30:F0, Offset 04h, bit 6) is set. If this bit is set
because of parity error and the D30:F0 SERR_EN bit (Offset 04h, bit 8) is also set, the ICH5 will
generate an NMI (or SMI# if NMI routed to SMI#).
NMI, or interrupt based on this bit getting set.
Command Register (offset 04h, bit 6) is set.
06
0080h
–
07h
®
ICH5 detected a parity error on the hub interface and the
—
R/WC.
Description
Intel
Attribute:
Size:
®
82801EB ICH5 / 82801ER ICH5R Datasheet
R/WC, RO
16 bits
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