LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 169

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

Note:
Note 1: SMSC Reserved registers have read/write capability. The default values set for these registers should be
SMSC DS – LPC47M14X
INT_G
Default = 0x00
on VCC POR, VTR
POR,
RESET and SOFT
RESET
Activate
OSC_CLK
Default = 0x00
on VTR POR
MPU-401
Base I/O Address
High Byte
Default = 0x03
on HARD RESET,
SOFT RESET, VCC
POR and VTR POR
MPU-401
Base I/O Address
Low Byte
Default = 0x30
on HARD RESET,
SOFT RESET, VCC
POR and VTR POR
The registers located in Logical Device A are runtime registers.
maintained unless otherwise specified.
NAME
NAME
NAME
HARD
Table 75 – USB Hub, Logical Device C [Logical Device Number = 0x0C]
Primary
Primary
REG INDEX
REG INDEX
Table 74 – MPU-401 [Logical Device Number = 0x0B]
REG INDEX
0xF2-
0xFF
0xF1
0x30
0xF0
R/W
0x60 R/W
0x61 R/W
R/W
Bit[7:1] Reserved
Bit[0]
Note:
Reserved – read as ‘0’
Bit [0]
Bits[7:1] Reserved (Writes are ignored and Reads
Note:
Bit [0] Reserved
Bit [1] OSC_CLK
0=48MHz clock is connected to the ICLK pin (default)
1=24MHz crystal is connected to the ICLK and OCLK
pins
Bits [7:2] Reserved
Bit[0] A8
Bit[1] A9
Bit[2] A10
Bit[3] A11
Bit[4] “0”
Bit[5] “0”
Bit[6] “0”
Bit[7] “0”
Bit[0] “0”
Bit[1] A1
Bit[2] A2
Bit[3] A3
Bit[4] A4
Bit[5] A5
Bit[6] A6
Bit[7] A7
Note: Bit[0] must be “0”.
INT_G Enable
This bit has read/write capability.
return 0)
This register has no dedicated function. The
user may use this register at their own
discretion.
0 = Disable Interrupt Generating Registers
from affecting the serial IRQ stream.
1 = Enable Interrupt Generating Registers to
See runtime registers at offset 0x54 and
0x55 for configuring Interrupt Generating
Registers.
Page 169
drive one or more frames low in the
SER IRQ stream
DEFINITION
DEFINITION
DEFINITION
STATE
NOTES
NOTES
Note 1
Note 1
Eng.
C
C
Rev. 03/19/2001