LPC47M142-NC Standard Microsystems (SMSC), LPC47M142-NC Datasheet - Page 37

• Manufacturer Part Number: LPC47M142-NC
• Manufacturer: Standard Microsystems (SMSC)

Specifications of LPC47M142-NC

• Lead Free Status / RoHS Status: Not Compliant

Should be set to a logical "0"
PS/2 Model 30 Mode
BIT 0 and 1 DATA RATE SELECT 0 and 1
These bits determine the data rate of the floppy controller. See Table 9 for the appropriate values.
BIT 2 NO PRECOMPENSATION
This bit can be set by software, but it has no functionality. It can be read by bit 2 of the DSR when in Model 30 register
mode. Unaffected by software reset.
BIT 3 - 7 RESERVED
Should be set to a logical "0"
Table 10 shows the state of the DENSEL pin. The DENSEL pin is set high after a hardware reset and is unaffected by
the DOR and the DSR resets.
6.5.2
During the Result Phase of certain commands, the Data Register contains data bytes that give the status of the
command just executed.
SMSC DS – LPC47M14X
STATUS REGISTER ENCODING
BIT NO.
7,6
1,0
5
4
3
2
RESET
COND.
SYMBOL
DS1,0
EC
SE
IC
H
N/A
7
Interrupt Code 00 - Normal termination of command.
Head Address The current head address.
Drive Select
Equipment
Seek End
N/A
NAME
Check
6
Table 13 – Status Register 0
N/A
5
command was properly executed and completed without
error.
01 - Abnormal termination of command.
execution was started, but was not successfully
completed.
10 - Invalid command. The requested command could
not be executed.
11 - Abnormal termination caused by Polling.
The FDC completed a Seek, Relative Seek or
Recalibrate command (used during a Sense Interrupt
Command).
The TRK0 pin failed to become a "1" after:
1. 80 step pulses in the Recalibrate command.
2. The Relative Seek command caused the FDC to
Unused. This bit is always "0".
The current selected drive.
Page 37
step outward beyond Track 0.
N/A
4
N/A
3
DESCRIPTION
NOPREC DRATE
N/A
2
SEL1
1
1
DRATE
The specified
SEL0
0
0
Command
Rev. 03/19/2001