NH82801IB S LA9M Intel, NH82801IB S LA9M Datasheet - Page 26

• Manufacturer Part Number: NH82801IB S LA9M
• Manufacturer: Intel

Specifications of NH82801IB S LA9M

• Lead Free Status / RoHS Status: Compliant

17.
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The AFTER_G3 bit provides the ability to program whether or not the system should
boot once power returns after a power loss event. If the policy is to not boot, the
system remains in an S5 state (unless previously in S4). The following wake events can
wake the system following a power loss by either RSMRST# going low and enabling by
default, the enable bits reside in the RTC well or the wake event is always enabled.
The ICH9 monitors both PWROK and RSMRST# to detect for power failures. If PWROK
goes low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
Correct section 10.1.45 Bit 0 definition
Correct selection 10.1.45 CIR5—Chipset Initialization Register 5 in the Datasheet
10.1.45 CIR5—Chipset Initialization Register 5
Offset Address: 1D40h–1D47h
Default Value:
Correct section 13.1.23 Bits 15:2 definition
Correct section 13.1.23 GEN1_DEC-LPC I/F Generic Decode Range 1 Register in the
Datasheet
13.1.23 GEN1_DEC-LPC I/F Generic Decode Range 1 Register
(LPC I/F-D31:F0)
Offset Address: 84h–87h
Default Value:
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss.
4. PCI Express Wake# Signal: The PCIEXPWAK_DIS bit is cleared by RSMRST# going
5. PME_B0: PME_B0_EN is in the RTC Well and is preserved after a power loss. The
6. PME: PME_EN: is in the RTC Well and is preserved after a power loss. The PME_STS
7. Host SMBUS: SMBUSALERT# or Slave Wake message is always enabled as Wake
8. ME Non-Maskable Wake: Always enabled as Wake Event.
63:0
Bit
(G3 state), the PWRBTN_STS bit is reset. When the ICH10 exits G3 after power
returns (RSMRST# goes high), the PWRBTN# signal is already high (because V
standby goes high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
wake event, it is important to keep this signal powered during the power loss
event. If this signal goes low (active), when power returns the RI_STS bit is set and
the system interprets that as a wake event.
Like PWRBTN_STS the RTC_STS bit is cleared when RSMRST# goes low.
low enabling PCI Express Ports to wake the platform after a power loss. The
PCIEXPWAK_STS bit is also cleared when RSMRST# goes low.
PME_B0_STS bit is also cleared when RSMRST# goes low.
bit is also cleared when RSMRST# goes low.
Event
Reserved
0000000000000000h
00000000h
Description
Attribute:
Size:
Attribute:
Size:
Power Well:
R/W
64-bit
R/W
32 bit
Core
Documentation Changes
Specification Update
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