ISP1581BD STEricsson, ISP1581BD Datasheet - Page 38
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ISP1581BD
Manufacturer Part Number
ISP1581BD
Description
Manufacturer
STEricsson
Datasheet
1.ISP1581BD.pdf
(80 pages)
Specifications of ISP1581BD
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Philips Semiconductors
Table 37:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
DMA Strobe Timing register: bit allocation
R/W
7
-
-
9.4.6 Task File registers (addresses: 40H to 4FH)
reserved
Table 38:
[1]
These registers allow direct access to the internal registers of an ATAPI peripheral
using PIO mode. The supported Task File registers and their functions are shown in
Table
CS0, DA2, DA1 and DA0 (see
Table 39:
Bit
7 to 5
4 to 0
Address (Hex)
1F0
1F1
1F2
1F3
1F4
1F5
1F6
1F7
3F6
3F7
Fig 5. Programmable strobe timing.
R/W
6
-
-
The cycle duration indicates the internal clock cycle (33.3 ns/cycle).
39. The correct peripheral register is automatically addressed via pins CS1,
DMA Strobe Timing register: bit description
Task File register functions
Symbol
-
DMA_
STROBE_
CNT[4:0]
R/W
5
-
-
Rev. 06 — 23 December 2004
ATA function
data (16-bits)
error/feature
sector count
sector number/LBA[7:0]
cylinder low/LBA[15:8]
cylinder high/LBA[23:16]
drive/head/LBA[27:24]
command
alternate status/command
drive address
Description
reserved.
These bits select the strobe duration for DMA_MODE = 03H
(see
representing the value of DMA_STROBE_CNT (see
4
Table
Table
x
33). The strobe duration is (N+1) cycles
40).
(N + 1) cycles
3
DMA_STROBE_CNT[4:0]
x
Hi-Speed USB peripheral controller
004aaa125
ATAPI function
data (16-bits)
error/feature
interrupt reason
reserved
cylinder low
cylinder high
drive select
status/command
alternate status/command
reserved
R/W
1FH
1FH
2
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
1
ISP1581
[1]
, with N
Figure
0
37 of 79
5).