LSISAS1064E LSI, LSISAS1064E Datasheet - Page 5
LSISAS1064E
Manufacturer Part Number
LSISAS1064E
Description
Manufacturer
LSI
Datasheet
1.LSISAS1064E.pdf
(30 pages)
Specifications of LSISAS1064E
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LSISAS1064E
Manufacturer:
ST
Quantity:
2 241
Company:
Part Number:
LSISAS1064E
Manufacturer:
LSI
Quantity:
996
Part Number:
LSISAS1064E
Manufacturer:
LSI
Quantity:
20 000
Part Number:
LSISAS1064E B1
Manufacturer:
LSILOGI
Quantity:
20 000
Company:
Part Number:
LSISAS1064E B3
Manufacturer:
LSI
Quantity:
59
Part Number:
LSISAS1064E B3
Manufacturer:
LSI
Quantity:
20 000
DB08-000275-03
LSISAS1064E PCI Express to 4-Port Serial Attached SCSI Controller
May 2006 - Version 2.0
Provides a scalable interface
–
–
–
Offers a maximum payload of 2 Kbytes
Supports serial, point-to-point interconnections between devices
–
–
Supports lane reversal and polarity inversion
Supports PCI Express Hot Plug
Supports Power Management
–
–
Uses a packetized and layered architecture
Achieves a high bandwidth per pin with low overhead and low latency
PCI Express is software compatible with PCI and PCI-X software
–
–
–
Provides 4 Kbytes of PCI Configuration address space per device
Supports posted and nonposted transactions
Provides quality of service (QOS) link configuration and arbitration
policies
Supports Traffic Class 0 and one virtual channel
Supports Message Signaled Interrupts (both MSI and MSI-X) as well
as INTx interrupt signaling for legacy PCI support
Supports end-to-end CRC (ECRC) and Advanced Error Reporting
Single-lane aggregate bandwidth of up to 0.5 Gbytes/s
(500 Mbytes/s)
Quad-lane aggregate bandwidth of up to 2.0 Gbytes/s
(2000 Mbytes/s)
8-lane aggregate bandwidth of up to 4.0 Gbytes/s
(4000 Mbytes/s)
Reduces the electrical load of the connection
Enables higher transmission and reception frequencies
Supports the PCI Power Management 1.2 specification
Supports Active State Power Management, including the L0, L0s,
and L1 states, by placing links in a power-savings mode during
times of no link activity
Leverages existing PCI device drivers
Supports the Memory, I/O, and Configuration address spaces
Supports memory read/write transactions, I/O read/write
transactions, and configuration read/write transactions
Copyright © 2004–2006 by LSI Logic Corporation. All rights reserved.
5 of 30