LH7A404 Sharp Electronics, LH7A404 Datasheet

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... DESCRIPTION The advent of 3G technology opens up a wide range of multimedia applications in mobile information appli- ances. The LH7A404 is designed from the ground up with a 32-bit ARM922 Core to provide high processing performance, low power consumption, and a high level of integration. Features include 80KB on-chip SRAM, fully static design, power management unit, low voltage (1 ...

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... WATCHDOG TIMER TIMER (3) GENERAL PURPOSE I/O (64) SYNCHRONOUS SERIAL PORT BATTERY MONITOR INTERFACE UART (3) IrDA INTERFACE USB DEVICE INTERFACE MULTIMEDIACARD/ SECURE DIGITAL INTERFACE AC97 CODEC INTERFACE SMART CARD INTERFACE (ISO7816) PWM (2) A/D TOUCH SCREEN CONTROLLER PS2 KEYBOARD/MOUSE INTERFACE INTERFACE (2) LH7A404-1 Data Sheet ...

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... K11 K12 L9 VSS I/O Ring Ground L10 L11 L12 M9 M10 M11 M12 T18 E7 E9 E14 G5 G16 VDDC Core Power P5 P16 T7 T12 T14 Data Sheet Table 2. LH7A404 Functional Pin List DESCRIPTION Version 1.5 LH7A404 RESET STANDBY OUTPUT I/O NOTES STATE STATE DRIVE 3 ...

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... LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL E6 E15 F5 F16 J16 VSSC Core Ground M5 R5 R16 T6 T15 Y17 VDDA Analog Power for PLL1 and PLL2 W17 V16 VSSA Analog Ground for PLL1 and PLL2 U15 W16 VDDAD Analog Power for A/D, Touch Screen Controller ...

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... System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL N19 D0 P20 D1 N18 D2 N20 D3 M16 D4 M18 D5 L18 D6 L17 D7 L19 D8 J19 D9 K17 D10 J18 D11 H19 D12 G20 D13 G19 D14 H17 D15 Data Bus F19 D16 E20 D17 E19 D18 ...

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... LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL N17 A2/SA0 M19 A3/SA1 M20 A4/SA2 L20 A5/SA3 M17 A6/SA4 K18 A7/SA5 K20 A8/SA6 Asynchronous Address Bus and Synchronous Address Bus K19 A9/SA7 J20 A10/SA8 H20 A11/SA9 J17 A12/SA10 H18 A13/SA11 ...

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... System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL C14 SCKE3 Clock Enable 3 for Synchronous Memory D14 SCLK Synchronous Memory Clock A13 nBLE0 Byte Lane Enable 0 U9 nBLE1 Byte Lane Enable 1 Y7 nBLE2 Byte Lane Enable 2 C13 nBLE3 Byte Lane Enable 3 ...

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... LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL V1 PC7 GPIO Port C7 Y11 PD0/LCDVD8 U10 PD1/LCDVD9 W12 PD2/LCDVD10 V11 PD3/LCDVD11 • GPIO Port D[7:0] • LCD Video Data Interface W11 PD4/LCDVD12 U11 PD5/LCDVD13 V12 PD6/LCDVD14 Y12 PD7/LCDVD15 Y9 PE0/LCDVD4 W10 PE1/LCDVD5 • ...

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... System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL • GPIO Port G2 Y3 PG2/nPCIOR • I/O Read Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • GPIO Port G3 U5 PG3/nPCIOW • I/O Write Strobe for PC Card (PCMCIA or CompactFlash) in Single or Dual Card mode • ...

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... USB Host Power Switch’s Enable pin. In response to T17 USBHPWR a fault contition, signalled on the nUSBHOVRCURR pin, the LH7A404 can assert this pin, which causes the power switch shut down. USB Host Overcurrent; The overcurrent input is used to indicate to the host a fault has occurred, resulting in current limiting ...

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... System-on-Chip Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL • Audio Codec (AC97) Clock C7 ACBITCLK • Audio Codec (ACI) Clock • Audio Codec (AC97) Output B7 ACOUT • Audio Codec (ACI) Output • Audio Codec (AC97) Synchronization A6 ACSYNC • Audio Codec (ACI) Synchronization • ...

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... LH7A404 Table 2. LH7A404 Functional Pin List (Cont’d) CABGA SIGNAL • ADC channel 3 U13 AN3/LR/Y- • Touch Screen Controller Lower Right • Touch Screen Controller Y-minus • ADC channel 4 V14 AN4/WIPER • Wiper input from 5-wire Touch Screen U14 VSS or VSSA ...

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... MUSTN3 MUSTN2 MUSTN2 MUSTN2 MUSTN1 MUSTN1 MUSTN1 MUSTN0 MUSTN0 MUSTN0 LCDFP LCDFP LCDFP LCDLP LCDLP LCDLP LCDM LCDM LCDM Version 1.5 LH7A404 COLOR AD-TFT/ TFT HR-TFT SINGLE DUAL PANEL PANEL LOW LOW CLSTN7 Intensity Intensity CLSTN6 BLUE4 BLUE4 CLSTN5 BLUE3 BLUE3 ...

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... LH7A404 Table 5. CABGA Numerical Pin List CABGA SIGNAL A1 PE7/SCDATEN 95 mV/ns A2 DACK1 95 mV/ns A3 DREQ0 A4 MMCDATA2 110 mV/ns A5 MMCCLK 110 mV/ns A6 ACSYNC 110 mV/ns A7 PF6/INT6/PCRDY1 110 mV/ns A8 PF2/INT2 110 mV/ns A9 PF0/INT0 110 mV/ns A10 nPWME1 95 mV/ns A11 SCCLK 95 mV/ns A12 DQM3 110 mV/ns ...

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... VSS 8 mA L10 VSS L11 VSS L12 VSS 12 mA L13 VDD 12 mA L16 VDD 12 mA L17 L18 L19 L20 A5/SA3 PA4 PA0/LCDVD16 Version 1.5 LH7A404 SLEW OUTPUT SIGNAL RATE DRIVE 100 mV/ 100 mV/ mV/ mV/ mV/ mV/ 110 mV/ 100 mV/ 110 mV/ 110 mV/ mV/ mV/ mV/ mV/ns ...

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... LH7A404 Table 5. CABGA Numerical Pin List (Cont’d) CABGA SIGNAL M3 PA2 110 mV/ns M4 PA3 110 mV/ns M5 VSSC M9 VSS M10 VSS M11 VSS M12 VSS M16 D4 95 mV/ns M17 A6/SA4 95 mV/ns M18 D5 95 mV/ns M19 A3/SA1 95 mV/ns M20 A4/SA2 95 mV/ns N1 PA7 110 mV/ns ...

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... Y12 PD7/LCDVD15 8 mA Y13 WIDTH0 8 mA Y14 AN9 8 mA Y15 AN1/UR/ Y16 AN0/UL/ Y17 VDDA 12 mA Y18 XTALIN 12 mA Y19 XTALOUT Y20 INTBOOT Version 1.5 LH7A404 SLEW OUTPUT SIGNAL RATE DRIVE 95 mV/ 110 mV/ 110 mV/ 110 mV/ 110 mV/ 110 mV/ mV/ mV/ mV/ mV/ mV/ns ...

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... Hz for the Real Time Clock counter using a ripple divider to save power. The 14.7456 MHz source is used to generate the main system clocks for the LH7A404 the source for PLL1 and PLL2, the primary clock for the peripher- als, and the source clock to the programmable clock (PGM) divider ...

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... AHB (AMBA AHB high speed 32-bit-wide data bus. The AMBA AHB is for high-performance, high-clock-fre- quency system modules. LH7A404 peripherals and memory with high band- width requirements are connected to the ARM922T processor and other bus masters using a multi-master AHB bus. These peripherals include the external mem- ...

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... SRAM, and to the control registers of the AHB and APB. The rest of the memory space is not used. The LH7A404 can boot from both internal and exter- nal devices. The selection is determined by the value of five pins at power-on reset as shown in Table 6. If boot- ing is from an external device (with INTBOOT = 0), refer to Table 7 ...

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... SROM (Initializes device MODE Register) Boot from internal Boot ROM; see Table 6 Data Sheet Table 6. Internal Boot Modes GPIO LATCHED LATCHED PA7 MEDCHG WIDTH1 See Table Table 7. External Boot Modes MEDCHG WIDTH1 Version 1.5 LH7A404 LATCHED LATCHED WIDTH0 INTBOOT WIDTH0 INTBOOT ...

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... LH7A404 Vectored Interrupt Controller (VIC) The LH7A404 has two VICs working together to manage interrupt requests from on-chip and off-chip sources. Each VIC performs these primary functions: • Determine if an interrupt source is disabled or can generate an FIQ or IRQ to the ARM core • Prioritize separate interrupt sources for simultaneous and nested processing • ...

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... System-on-Chip Embedded SRAM The LH7A404 incorporates 80KB of embedded SRAM. This embedded memory is used for storing code, data, or LCD frame data and is contiguous with external SDRAM. The 80KB is large enough to store a QVGA frame (320 × 240 bits per pixel, equivalent to 70KB of information. ...

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... LH7A404 SD/MMC INTERFACE DESCRIPTION The SD/MMC controller uses the three-wire signal bus (clock, command, and data) to input and output data to and from the MMC, and to configure and acquire status information from the card. The SD con- troller differs in that it has four data lines instead of one. ...

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... Open Host Controller Interface Specification (Open- HCI) Rev. 1.0 Compliant • Universal Serial Bus Specification 2.0 Full Speed compatible • Supports Low Speed and High Speed USB devices • Root Hub has two Downstream Ports • DMA functionality. Version 1.5 LH7A404 25 ...

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... Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A404 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK ...

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... A/D Converter with Brownout Detector and Touch Screen Controller The LH7A404 includes an A/D Converter (ADC) with integrated Touch Screen Controller (TSC) and brown- out detector. The TSC is a complete interface to a Touch Screen for portable personal devices. It com- ...

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... Features of the WDT: • Timing derived from the system clock • 16 programmable time-out periods: 2 clock cycles • Generates a system reset (resets LH7A404 FIQ interrupt whenever a time-out period is reached • Software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes • ...

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... System-on-Chip ELECTRICAL SPECIFICATIONS IMPORTANT: The LH7A404 is an electrostatic discharge (ESD) sensitive device. ESD protection circuitry internal to the LH7A404 has been added to reduce ESD susceptibility. Appropriate ESD precautions are still required during handling to prevent degradation or failure due to high electrostatic discharges. System design practices should be evaluated to prevent LH7A404 ESD voltages from exceeding the maximum rated voltage as specified in this data sheet ...

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... Clock Period (1/FCLK) Clock Frequency (FCLK) 70°C Clock Period (1/FCLK) Clock Frequency (FCLK) 85°C Clock Period (1/FCLK) NOTE: *LH7A404-N0E-000-xx and LH7A404-N0F-000-xx only. Table 8 is representative of a typical device. Guaranteed values are in the Recommended Operating Conditions table. 255 250 245 240 235 ...

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... Input Leakage Current, with pullup resistors IOZ Output Tri-state Leakage Current ISTARTUP Startup Current CIN Input Capacitance COUT Output Capacitance LH7A404-N0E-000-XX AND LH7A404-N0F-000-XX ONLY IACTIVE Active Current (Operating Current) IHALT Halt Current ISTANDBY Standby Current LH7A404-N0E-092-XX AND LH7A404-N0F-092-XX ONLY IACTIVE Active Current (Operating Current) ...

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... LH7A404 Analog-To-Digital Converter Electrical Characteristics Table 9 shows the derated specifications for extended temperature operation. See Figure 6 for the ADC transfer characteristics. Table 9. ADC Electrical Characteristics PARAMETER A/D Resolution Throughput Conversion Acquisition Time Data Format Clk Frequency Differential Non-Linearity (DNL) Integral Non-Linearity (INL) ...

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... Input and Output Timing Reference Levels Data Sheet IDEAL TRANSFER CURVE TRANSFER CURVE INTEGRAL NON-LINEARITY 1015 1016 1017 1018 1019 Figure 6. ADC Transfer Characteristics RATING UNIT 3.0 to 3.6 V 1.7 to 1.9 V VSS VDD/2 V Version 1.5 LH7A404 OFFSET GAIN ERROR ERROR ACTUAL 1020 1021 1022 1023 1024 LH7A404-154 33 ...

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... Core Current IIO I/O Current NOTES: 1. FCLK = 200 MHZ pertains to LH7A404-N0E-000-xx and LH7A404-N0F-000-xx 2. FCLK = 266 MHz pertains to LH7A404-N0E-092-xx and LH7A404-N0F-092-xx. 34 PERIPHERAL CURRENT CONSUMPTION In addition to the modal current consumption, Table 10 shows the typical current consumption for each of the on-board peripheral blocks. The values were determined with the peripheral clock running at 200 MHz, typical conditions, and no I/O loads ...

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... OUTPUT SIGNAL (O) INPUT SIGNAL (I) Data Sheet For outputs from the LH7A404, tOVXXX (e.g. tOVA) represents the amount of time for the output to become valid from the rising edge of the reference clock signal. Maximum requirements for tOVXXX are shown in Table 12. The signal tOHXXX (e.g. tOHA) represents the amount of time the output must be held valid after the rising edge of the reference clock signal ...

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... LH7A404 SIGNAL TYPE LOAD SYMBOL ASYNCHRONOUS MEMORY INTERFACE SIGNALS (+ [wait states × HCLK period]) Output 50 pF tRC A[27:0] Output 50 pF tWC — — tWS tDVWE tDHWE Output 50 pF tDVBE tDHBE tDSCS D[31:0] tDHCS tDSOE Input — tDHOE tDSBE tDHBE tCS nCS[7:0] ...

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... NOTES: 1. Register BCRx:WST1 = 0b000 2. The ‘x/x’ in the MIN./MAX. indicates (LH7A404-N0E-092-xx and H7A404-N0F-092-xx)/ (LH7A404-N0E-000-xx and LH7A404-N0F-000-xx), respectively. 3. ‘tcyc’ is the period of one MMC Clock 4. ‘tcyc’ is the period of one AC97 Clock 5. ‘nC’ in the MIN./MAX. columns indicates the number of system clock (HCLK) periods after valid address 6 ...

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... Figure 8. External Asynchronous Memory Write, Zero Wait States (BCRx:WST1 = 0b000 tWC VALID ADDRESS tDVWE, tDHWE, tDVBE tDHBE VALID DATA tAVCS tCS nCS Valid tAVWE tWE tCSHWE nWE Valid WRITE EDGE tAVBE tBEW tCSHBE nBLE Valid Version 1.5 32-Bit System-on-Chip 4 tAHCS LH7A404-10 Data Sheet ...

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... Figure 9. External Asynchronous Memory Write, Four Wait States (BCRx:WST1 = 0b100) Data Sheet VALID ADDRESS VALID DATA nCSx Valid nWE Valid nBLE Valid WAIT WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 STATE 4 tWS tWS tWS tWS Version 1.5 LH7A404 7 8 WRITE EDGE LH7A404-189 39 ...

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... Figure 10. External Asynchronous Memory Read, Zero Wait States (BCRx:WST1 = 0b000 tRC tAHOE, tAHBE VALID ADDRESS VALID DATA tDSCS tAVCS tCS nCS Valid tDSOE tAVOE tOE nOE Valid tDSBE tAVBE tBER nBLE Valid Version 1.5 32-Bit System-on-Chip 4 tAHCS, DATA LATCHED HERE tDHCS tDHOE tDHBE LH7A404-190 Data Sheet ...

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... Figure 11. External Asynchronous Memory Read, Four Wait States (BCRx:WST1 = 0b100) Data Sheet VALID ADDRESS nCSx Valid nOE Valid nBLE Valid VALID DATA WAIT WAIT WAIT STATE 1 STATE 2 STATE 3 tWS tWS tWS Version 1.5 LH7A404 WAIT STATE 4 4 WAIT STATES, DATA LATCHED tWS HERE LH7A404-12 41 ...

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... SMC transaction by either Wait States or nWAIT delays can cause refresh failure for the SDRAM, and may cause SDRAM data loss. Version 1.5 32-Bit System-on-Chip SQ-0 nWAIT END DELAY CYCLE LH7A404-203 1 MIN. MAX. UNIT 0 29 HCLK periods 4 HCLK periods ...

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... SQ-0 SQ-4 SQ-3 SQ-2 nWAIT nWAIT nWAIT WSD-1 WSD-0 DELAY DELAY DELAY DELAY DELAY tA_nWAIT SI SI WSD-3 WSD-2 WSD-1 WSD-0 DELAY DELAY DELAY DELAY CYCLE Version 1.5 LH7A404 tDD_nWAIT_nCS(x) tDD_nWAIT_nOE) SQ-1 SQ-0 nWAIT nWAIT END DELAY DELAY CYCLE LH7A404-204 END LH7A404-205 43 ...

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... SQ-1 SQ-0 SQ-4 SQ-3 SQ-2 SQ-1 WSD-0 nWAIT nWAIT nWAIT nWAIT DELAY DELAY DELAY DELAY DELAY DESCRIPTION Version 1.5 32-Bit System-on-Chip SQ-0 nWAIT END DELAY CYCLE LH7A404-206 1 MIN. MAX. UNIT 0 29 HCLK periods 4 HCLK periods 3 HCLK periods 2 HCLK periods Data Sheet ...

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... Figure 16. nWAIT Write Sequence (BCRx:WST1 = 4); Ignored and Queued nWAIT Delays Data Sheet tA_nWAIT SQ-3 SQ-2 SQ-1 SQ-0 SQ-4 SQ-3 SQ-2 nWAIT nWAIT nWAIT WSD-1 WSD-0 DELAY DELAY DELAY DELAY DELAY Version 1.5 LH7A404 tDD_nWAIT_nCS(x) tDD_nWAIT_nWE SQ-1 SQ-0 nWAIT nWAIT END DELAY DELAY CYCLE LH7A404-207 45 ...

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... Transaction Sequence DELAY NOTES: SQ: nWAIT Sampled and Queued SI: nWAIT Sampled and Ignored Figure 17. nWAIT Write Sequence (BCRx:WST1 = 4); nWAIT Has No Effect On Current Transaction 46 tA_nWAIT SI SI WSD-3 WSD-2 WSD-1 WSD-0 DELAY DELAY DELAY DELAY CYCLE Version 1.5 32-Bit System-on-Chip END LH7A404-208 Data Sheet ...

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... Figure 19. Synchronous Bank Activate and Write Data Sheet t OHXXX READ t OVB t OVXXX BANK, tISD tIHD COLUMN tOVA DATA n DATA Figure 18. Synchronous Burst Read tOVC tOVXXX tOHXXX ACTIVE tOHA BANK, ROW tOVA Version 1.5 LH7A404 DATA DATA LH7A404-13 WRITE BANK, COLUMN DATA tOVD tOHD LH7A400-24 47 ...

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... SSP and the external slave device drive their output data on the rising edge of the clock and latch data from the other device on the falling edge. See Figure 20 and Figure 21. MSB LSB BITS MSB BITS Version 1.5 32-Bit System-on-Chip LH7A404-24 LSB LH7A404-25 Data Sheet ...

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... MSB SSPTXD MSB NOTE undefined. Figure 24. Motorola SPI Frame Format (Single Transfer) with SPO = 0 and SPH = 1 Data Sheet in single and continuous modes. See Figures 22 through 29 BITS LSB MSB BITS BITS Version 1.5 LH7A404 LSB Q LSB LH7A404-26 MSB LH7A404-27 LSB Q LSB LH7A404-28 49 ...

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... SSPRXD MSB SSPTXD MSB NOTE undefined. Figure 27. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 0 50 LSB MSB BITS LSB MSB BITS BITS Version 1.5 32-Bit System-on-Chip LSB MSB LH7A404-29 LSB MSB LH7A404-30 Q LSB LSB LH7A404-31 Data Sheet ...

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... Figure 28. Motorola SPI Frame Format (Continuous Transfer) with SPO = 1 and SPH = 0 SSPCLK nSSPFRM SSPRXD Q MSB SSPTXD MSB NOTE undefined. Figure 29. Motorola SPI Frame Format (Single Transfer) with SPO = 1 and SPH = 1 Data Sheet MSB LSB BITS BITS Version 1.5 LH7A404 MSB LH7A404-32 LSB Q LSB LH7A404-33 51 ...

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... The returned data can bits in length, making the total frame length between bits. See Figure 30 and Figure 31. LSB 0 MSB LSB BITS OUTPUT DATA MSB LSB 8-BIT CONTROL LSB Version 1.5 32-Bit System-on-Chip LH7A404-34 MSB LH7A404-35 Data Sheet ...

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... SSPCLK (Programmable CLOCK phase) SSPTX SSPRX SSPFRM (Programmable FRAME phase and duration) Data Sheet tCLK CLOCK CLOCK PHASE 1 PHASE 2 tOVTX tOHTX BITn BITn-1 OUTPUT OUTPUT tISRX tIHRX BITn BITn-1 INPUT INPUT tOHFRM tOVFRM Figure 32. General SSP Timing Version 1.5 LH7A404 LH7A404-199 53 ...

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... Common Memory 0 1 Attribute Memory None 54 PRECHARGE ACCESS TIME TIME (See Note 1) (See Note 1) (See Note 1) ADDRESS tOVDREG tOHDREG tOVCEx tOHCEx tOVPCD tOHPCD DATA tISD tIHD tOVOE tOHOE Figure 33. PCMCIA Read Transfer Version 1.5 32-Bit System-on-Chip HOLD TIME Data Sheet LH7A404-15 ...

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... Figure 35. PCMCIA Precharge, Access, and Hold Waveform Data Sheet PRECHARGE ACCESS TIME TIME (See Note 1) (See Note 1) (See Note 1) ADDRESS tOVDREG tOHDREG tOVCEx tOHCEx tOVPCD DATA tOVD tOHD tOVWE tOHWE I/O Figure 34. PCMCIA Write Transfer ACCESS PRECHARGE Version 1.5 HOLD TIME LH7A404-16 HOLD LH7A404-194 LH7A404 55 ...

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... AC97 interface Data Setup and Hold. tMMCCLK tOVCMD tOHCMD tOVDAT tOHDAT Figure 36. MMC Command/Data Write tISCMD tIHCMD tISDAT tIHDAT Figure 37. MMC Command/Data Read tACBITCLK tOVAC97 tOHAC97 tISAC97 tIHAC97 Figure 38. AC97 Data Setup and Hold Version 1.5 32-Bit System-on-Chip LH7A404-19 LH7A404-20 LH7A404-21 Data Sheet ...

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... The timing for the Audio Codec Interface are shown in Figure 39 and Figure 40. Transmit data is clocked on the rising edge of ACBITCLK (whether transmitted by the LH7A404 ACI or by the external codec chip); receive data is clocked on the falling edge. This allows full-speed, full duplex operation. ...

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... LH7A404 58 Figure 42. STN Horizontal Timing Version 1.5 32-Bit System-on-Chip Data Sheet ...

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... System-on-Chip Data Sheet Figure 43. STN Vertical Timing Version 1.5 LH7A404 59 ...

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... LH7A404 60 Figure 44. TFT Horizontal Timing Version 1.5 32-Bit System-on-Chip Data Sheet ...

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... System-on-Chip Data Sheet Figure 45. TFT Vertical Timing Version 1.5 LH7A404 61 ...

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... FOR HR-TFT) LCDSPL V3 (LINE START PULSE LEFT) V2 LCDLP (HORIZONTAL SYNC PULSE) U3 LCDCLS V5 LCDPS W3 LCDREV NOTE: Circled numbers are LH7A404 pin numbers. Figure 46. AD-TFT and HR-TFT Horizontal Timing LCDSPS T4 (Vertical Sync) LCDHRLP V2 (Horizontal Sync) LCDVD (LCD Data) V3 LCDSPL 62 1 AD-TFT or HR-TFT HORIZONTAL LINE ...

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... System-on-Chip Clock and State Controller (CSC) Waveforms Figure 48 shows the behavior of the LH7A404 when coming out of Reset or Power-On. Table 13 gives the timing parameters. At Power-On, nPOR must be held LOW until the 32.768 kHz oscillator is stable, and must be deasserted at least two 1 Hz clock periods before the WAKEUP signal is asserted. Once the 14.7456 MHz oscillator is stable, the PLLs require 250 µ ...

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... Hz Periods* XTAL32 Periods XTAL32 Periods* Version 1.5 32-Bit System-on-Chip tA_WKUP tDA_WKUP_CLKEN LH7A404-202 DESCRIPTION nPOR to nRESETOUT assertion delay nPOR to nRESETOUT deassertion delay nPOR deassertio to WAKEUP assert delay WAKEUP assertion time nURESET assertion to CLKEN deassertion delay WAKEUP to CLKEN assertion delay Data Sheet ...

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... XTAL32 Periods* nURESET assertion time XTAL32 Periods* nURESET deassertion to WAKEUP assertion delay XTAL32 Periods* WAKEUP assertion time 4 XTAL32 Periods* nURESET assertion to CLKEN deassertion delay 4 XTAL32 Periods* WAKEUP to CLKEN assertion delay Version 1.5 LH7A404 tA_WKUP tDA_WKUP_CLKEN LH7A404-201 DESCRIPTION 65 ...

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... XTAL32 Periods nPWRFL assertion time 1 Hz Periods nPWRFL deassertion to WAKEUP assertion delay XTAL32 Periods WAKEUP assertion time 4 XTAL32 Periods nPWRFL assertion to CLKEN deassertino delay 4 XTAL32 Periods WAKEUP to CLKEN assertion delay Version 1.5 32-Bit System-on-Chip tA_WKUP tDA_WKUP_CLKEN LH7A404-200 DESCRIPTION Data Sheet ...

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... The switching speed of the CMOS circuitry within the SoC depends partly on Tj, and the lower the operating tem- perature, the faster the CMOS circuits will switch. INTERNAL TO THE LH7A404 EXTERNAL TO THE LH7A404 NOTES parallel-resonant type crystal. (See table) 2 ...

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... LH7A404 INTERNAL TO THE LH7A404 EXTERNAL TO THE LH7A404 NOTES parallel-resonant type crystal. (See table) 2. The nominal values for C1 and C2 shown are for a crystal specified load capacitance (CL). 3. The values for C1 and C2 are dependent upon the cystal's specified load capacitance and PCB stray capacitance. ...

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... System-on-Chip Printed Circuit Board Layout Practices LH7A404 POWER SUPPLY DECOUPLING The LH7A404 has separate power and ground pins for different internal circuitry sections. The VDD and VSS pins supply power to I/O buffers, while VDDC and VSSC supply power to the core logic, and VDDA/VSSA supply analog power to the PLLs ...

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... LH7A404 PACKAGE SPECIFICATIONS 324-BALL CABGA TOP VIEW A1 BALL PAD CORNER BOTTOM VIEW (324 solder balls 0.90 NOTES: 1. Dimensions in mm. 2. The A1 ball indicator should be used for proper package orientation. The device marking orientation may change with respect to the A1 ball indicator. Figure 55. 324-Ball CABGA Package Specification 70 0 ...

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... System-on-Chip 324-BALL CABGA FOOTPRINT TOP VIEW A1 BALL PAD CORNER 0.90 NOTES: 1. Dimensions in mm. 2. Recommended PCB pad diameter: 0.30 mm. Figure 56. 324-Ball CABGA Package PCB Footprint Data Sheet Package PCB Footprint Version 1.5 LH7A404 0.80 324CABGA-FP 71 ...

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... LH7A404 DEVICE MARKING AND PACKING SPECIFICATIONS SHARP’s LH7A404 in finished form are marked in a manner similar to Figure 58. See Figure 55 for proper device orientation. Packing Specifications SHARP’s LH7A404 are packed and shipped in a manner similar to that in Figure 59. When the number of devices being shipped reqires more than one Device Packing Box, a Shipping box will be used ...

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... RETAINER TRAY (Containing Parts) RETAINER TRAY (Empty) LABEL Sharp Microelectronics Part #: Lot #: Date Code : Qty : * Data Sheet PADDING (Top) (Sealed with Dessicant) PADDING (Bottom) Figure 59. LH7A404 Shipment Packaging Version 1.5 FOIL DEVICE PACKING BOX SHIPPING BOX (Holds packing boxes) LH7A404 MCU PACKING 73 ...

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... LH7A404 CONTENT REVISIONS This document contains the following changes to content, causing it to differ from previous versions. PAGE PARAGRAPH OR DATE NO. ILLUSTRATION 3-20 Tables Figure 30 9/16/03 54-56 Figure 33 Figure 36 1 Text 2 Figure 1 3-12 Table 1 12-18 Tables 3-14 26, 27, Text 11/15/03 30, 38 “Recommended Operating 33 Conditions” ...

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... Corrected PCMCIA D[31:0] timing values tISD and tIHD. Revised drawings to match SRAM datasheet parameter naming conventions. Added figure and text defining WAKEUP signal requirements. Added package footprint drawing. Added 266 MHz specifications. Version 1.5 LH7A404 μs if supplies remain 75 ...

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... Figure 48 65 Figure 50 Low Operating Tempera- 67 tures and Noise Immunity All Footing 1 Features 1, 29 Operating Conditions 3 Table 2 Recommended Operating 10-14-05 Conditions for LH7A404- 30 N0E-092-xx/LH7A404-N0F- 092-xx 32 Table 9 Current Consumption by 34 Mode 36 Table 12 64 Figure 49 76 Table 19. Record of Revisions SUMMARY OF CHANGES Rolled revision to Version 1.2. ...

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... System-on-Chip PAGE PARAGRAPH OR DATE NO. ILLUSTRATION All Footing 1 Features 12 Notes Recommended Operating Conditions for LH7A404- 29 N0E-000-xx/LH7A404-N0F- 000-xx Recommended Operating Conditions for LH7A404- 30 N0E-092-xx/LH7A404-N0F- 092-xx 32 Table 9 4-14-06 36 Table Figure 8 - Figure 11 53 Figure Figure 41 - Figure 47 63 Text 63 Table 13 64 Figure 49 70 Figure 55 All ...

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... LH7A404 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP’s product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ...