LH7A404 Sharp Electronics, LH7A404 Datasheet - Page 69

• Manufacturer Part Number: LH7A404
• Manufacturer: Sharp Electronics

Specifications of LH7A404

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.71V
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.89V
• Package Type: CABGA
• Pin Count: 324
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Not Compliant

32-Bit System-on-Chip
Printed Circuit Board Layout Practices
LH7A404 POWER SUPPLY DECOUPLING
for different internal circuitry sections. The VDD and
VSS pins supply power to I/O buffers, while VDDC and
VSSC supply power to the core logic, and VDDA/VSSA
supply analog power to the PLLs.
with a low impedance path to the corresponding board
power supply. Likewise, the VSS and VSSC pins must be
provided with a low impedance path to the board ground.
using at least one 0.1 μF high frequency capacitor
located as close as possible to a VDDx-VSSx pin pair
on each of the four sides of the chip. If room on the cir-
cuit board allows, add one 0.01 μF high frequency
capacitor near each VDDx-VSSx pair on the chip.
circuit board traces connecting to the chip VDDx-VSSx
pins must be kept to less than half an inch (12.7 mm)
per capacitor lead. There must be one bulk 10 μF
capacitor for each power supply placed near one side
of the chip.
REFERENCE PLL, VDDA, VSSA FILTER
cuitry. VSSA is the ground return path for the PLL cir-
cuit. SHARP recommends a low-pass filter attached as
shown in Figure 54. The values of the inductor and
capacitors are not critical. The low-pass filter prevents
high frequency noise from adversely affecting the PLL
circuits. The distance from the IC pin to the high fre-
quency capacitor should be as short as possible.
Data Sheet
(SOURCE)
The LH7A404 has separate power and ground pins
Each of the VDD and VDDC pins must be provided
Each power supply must be decoupled to ground
To be effective, the capacitor leads and associated
The VDDA pins supply power to the chip PLL cir-
VDDC
Figure 54. VDDA, VSSA Filter Circuit
10 µH
22 µF
+
0.1 µF
VSSAx
VDDC
VDDAx
LH7A404
LH7A404-169
Version 1.5
UNUSED INPUT SIGNAL CONDITIONING
consumption. Unused inputs without internal pull-up or
pull-down resistors should be pulled up or down exter-
nally, to tie the signal to its inactive state. SHARP rec-
ommends using no larger than 33 kΩ.
that carry these signals are unused, software can pro-
gram these signals as outputs, eliminating the need for
pull-ups or pull-downs. Power consumption may be
higher than expected until software completes pro-
gramming the GPIO. Some LH7A404 inputs have inter-
nal pull-ups or pull-downs. If unused, these inputs do
not require external conditioning.
OTHER CIRCUIT BOARD LAYOUT PRACTICES
cuit trace interconnection length must therefore be
reduced to minimize overshoot, undershoot and reflec-
tions caused by transmission line effects of these fast
output switching times. This recommendation particu-
larly applies to the address and data buses.
consider all device loads and capacitances due to the
circuit board traces. Capacitance due to the traces will
depend upon a number of factors, including the trace
width, dielectric material the circuit board is made from
and proximity to ground and power planes.
cuit board layout becomes more critical in systems with
higher capacitive loads. As these capacitive loads
increase, transient currents in the power supply and
ground return paths also increase.
Floating input signals can cause excessive power
Some GPIO signals may default to inputs. If the pins
All outputs have fast rise and fall times. Printed cir-
When considering capacitance, calculations must
Attention to power supply decoupling and printed cir-
LH7A404
69