MC68331CEH16 Freescale, MC68331CEH16 Datasheet
MC68331CEH16
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MC68331CEH16 Summary of contents
Page 1
... High-density complementary metal-oxide semiconductor (HCMOS) architecture makes the basic power consumption of the MCU low. Power consumption can be minimized by stopping the system clock. The CPU32 instruction set includes a low-power stop (LPSTOP) command that efficiently implements this capability. For More Information On This Product, Go to: www.freescale.com Order this document by MC68331TS/D Rev. 2 MC68331 ...
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... MHz 2 pc tray 44 pc tray 20 MHz 2 pc tray 44 pc tray 16 MHz 2 pc tray 44 pc tray 20 MHz 2 pc tray 44 pc tray Go to: www.freescale.com Order Number SPAKMC331CFC16 MC68331CFC16 SPAKMC331CFC20 MC68331CFC20 SPAKMC331VFC16 MC68331VFC16 SPAKMC331VFC20 MC68331VFC20 SPAKMC331MFC16 MC68331MFC16 SPAKMC331MFC20 MC68331MFC20 SPAKMC331CFV16 ...
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... Pin Function ..............................................................................................................................52 5.3 QSM Registers .......................................................................................................................... 53 5.4 QSPI Submodule .......................................................................................................................56 5.5 SCI Submodule .........................................................................................................................64 6 General-Purpose Timer Module 6.1 Overview ...................................................................................................................................70 6.2 Capture/Compare Unit ..............................................................................................................71 6.3 Pulse-Width Modulator ..............................................................................................................74 6.4 GPT Registers ........................................................................................................................... 75 7 Summary of Changes For More Information On This Product, MC68331TS/D TABLE OF CONTENTS Go to: www.freescale.com Page ...
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... Two 16-Bit Free-Running Counters With One Nine-Stage Prescaler — Three Input Capture Channels — Four Output Compare Channels — One Input Capture/Output Compare Channel — One Pulse Accumulator/Event Counter Input — Two Pulse-Width Modulation Outputs — Optional External Clock Input For More Information On This Product to: www.freescale.com MC68331TS/D ...
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... PQS2/SCK SCK PQS1/MOSI MOSI PQS0/MISO MISO BKPT/DSCLK IFETCH/DSI IPIPE/DSO For More Information On This Product, MC68331TS/D SELECTS GPT IMB QSM CPU32 Figure 1 MCU Block Diagram Go to: www.freescale.com CHIP CSBOOT BR ADDR23/CS10 BG PC6/ADDR22/CS9 BGACK PC5/ADDR21/CS8 CS[10:0] PC4/ADDR20/CS7 PC3/ADDR19/CS6 FC2 PC2/FC2/CS5 FC1 PC1/FC1/CS4 FC0 PC0/FC0/CS3 ...
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... PQS0/MISO 43 PQS1/MOSI 44 PQS2/SCK 45 PQS3/PCS0/SS 46 PQS4/PCS1 47 PQS5/PCS2 48 PQS6/PCS3 Figure 2 MC68331 132-Pin QFP Pin Assignments For More Information On This Product, 6 MC68331 Go to: www.freescale.com V DD 116 115 BGACK/CS2 114 BG/CS1 113 BR/CS0 112 CSBOOT 111 DATA0 110 DATA1 109 DATA2 108 DATA3 V DD 107 ...
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... PGP5/OC3/OC1 PGP4/OC2/OC1 29 30 PGP3/OC1 31 PGP2/IC3 32 PGP1/IC2 33 PGP0/IC1 Figure 3 MC68331 144-Pin QFP Pin Assignments For More Information On This Product, MC68331TS/D MC68331 Go to: www.freescale.com 109 108 107 106 PE4/AS 105 PE6/SIZ0 104 PE7/SIZ1 103 R/W 102 PF0/MODCLK 101 PF1/IRQ1 100 PF2/IRQ2 99 PF3/IRQ3 98 ...
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... The standardized modules in the MCU communi- cate with one another and with external components through the IMB. The IMB in the MCU uses 24 address and 16 data lines. For More Information On This Product, 8 GPT SIM RESERVED QSM 331 ADDRESS MAP Figure 4 MCU Address Map Go to: www.freescale.com MC68331TS/D ...
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... — — — — to: www.freescale.com Discrete Port I/O Designation O — O PC[6:3] — — I/O PE5 I/O PE2 — — — — — — — — — — — — — — — — I/O PE4 I/O PE1 I/O PE0 — — ...
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... Internal Module Power (Source and Drain) Table 4 MCU Driver Types Description MCU Module SIM SIM SIM SIM SIM SIM CPU32 SIM SIM SIM SIM SIM SIM Go to: www.freescale.com Discrete Port I/O Designation — — I/O PQS2 I/O PE[7:6] — — I/O PQS7 Special — ...
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... BGACK Indicates that an external device has assumed bus mastership BKPT Signals a hardware breakpoint to the CPU BR Indicates that an external device requires bus mastership System clock output Select external devices at programmed addresses Go to: www.freescale.com Signal Type Active State Input 0 Input Serial Clock Input ...
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... Indicates the number of bytes to be transferred during a bus cycle SS Causes serial transmission when QSPI is in slave mode; causes mode fault in master mode TSC Places all output drivers in a high-impedance state TXD Serial output from the SCI XFC Connection for external phase-locked loop filter capacitor Go to: www.freescale.com Function MC68331TS/D ...
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... Freescale Semiconductor, Inc. For More Information On This Product, MC68331TS/D Go to: www.freescale.com 13 ...
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... SUPV bit in the SIMCR. For More Information On This Product, 14 XTAL CLKOUT EXTAL MODCLK CHIP SELECTS EXTERNAL BUS RESET TSC FREEZE/QUOT Figure 5 SIM Block Diagram Go to: www.freescale.com 300 S(C)IM BLOCK MC68331TS/D ...
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... CHIP-SELECT BASE 0 (CSBAR0) CHIP-SELECT OPTION 0 (CSOR0) CHIP-SELECT BASE 1 (CSBAR1) CHIP-SELECT OPTION 1 (CSOR1) CHIP-SELECT BASE 2 (CSBAR2) CHIP-SELECT OPTION 2 (CSOR2) CHIP-SELECT BASE 3 (CSBAR3) CHIP-SELECT OPTION 3 (CSOR3) CHIP-SELECT BASE 4 (CSBAR4) Go to: www.freescale.com 0 NOT USED NOT USED NOT USED (SYPCR) NOT USED NOT USED NOT USED ...
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... CHIP-SELECT BASE 7 (CSBAR7) CHIP-SELECT OPTION 7 (CSOR7) CHIP-SELECT BASE 8 (CSBAR8) CHIP-SELECT OPTION 8 (CSOR8) CHIP-SELECT BASE 9 (CSBAR9) CHIP-SELECT OPTION 9 (CSOR9) CHIP-SELECT BASE 10 (CSBAR10) CHIP-SELECT OPTION 10 (CSOR10) NOT USED NOT USED NOT USED NOT USED Go to: www.freescale.com 0 NOT USED NOT USED NOT USED NOT USED MC68331TS/D ...
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... When FREEZE is asserted, the bus monitor continues to operate When FREEZE is asserted, the bus monitor is disabled. For More Information On This Product, MC68331TS/D RESET STATUS HALT MONITOR BUS MONITOR SOFTWARE WATCHDOG TIMER PERIODIC INTERRUPT TIMER SHEN SUPV to: www.freescale.com RESET REQUEST BERR RESET REQUEST IRQ[7:1] 300 SYS PROTECT BLOCK $YFFA00 IARB ...
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... Show cycles disabled, external arbitration enabled Show cycles enabled, external arbitration disabled Show cycles enabled, external arbitration enabled Show cycles enabled, external arbitration enabled, internal activity is halted by a bus grant SWE SWP SWT 1 MODCLK 0 Go to: www.freescale.com $YFFA21 HME BME BMT MC68331TS/D ...
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... The halt monitor reset can be inhib- ited by the HME bit in the SYPCR. For More Information On This Product, MC68331TS/D SWT Ratio Bus Monitor Time-out Period 64 System Clocks 32 System Clocks 16 System Clocks 8 System Clocks Go to: www.freescale.com 19 ...
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... The following table shows what interrupt request level is asserted when a periodic interrupt is generat- ed PIT interrupt and an external IRQ signal of the same priority occur simultaneously, the PIT in- terrupt is serviced first. The periodic timer continues to run when the interrupt is disabled. For More Information On This Product MODCLK SWP PIRQL to: www.freescale.com $YFFA27 $YFFA22 0 PIV MC68331TS/D ...
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... Interrupt Request Level 1 010 Interrupt Request Level 2 011 Interrupt Request Level 3 100 Interrupt Request Level 4 101 Interrupt Request Level 5 110 Interrupt Request Level 6 111 Interrupt Request Level PTP 0 0 MODCLK 0 0 PIT Period = [(PITM)(Prescaler)(4)]/EXTAL Go to: www.freescale.com $YFFA24 0 PITM ...
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... For More Information On This Product DDSYN 1 XFC 0 DDSYN XFC PIN LOW-PASS FILTER W FEEDBACK DIVIDER Y X SYSTEM CLOCK CONTROL Minimum external clock period = minimum external clock high/low time Go to: www.freescale.com 0 SSI VCO SYSTEM CLKOUT CLOCK SYS CLOCK BLOCK 32KHZ MC68331TS/D ...
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... Clock source is determined by the logic state of the MODCLK pin during reset. SYNCR —Clock Synthesizer Control Register RESET For More Information On This Product, MC68331TS/D pin to ensure stable operating frequency. DDSYN [4(Y + 1)(2 SYSTEM REFERENCE EDIV to: www.freescale.com $YFFA04 SLIMP SLOCK RSTEN STSIM STEXT ...
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... Ports are accessed through the use of asynchronous cycles controlled by the data transfer (SIZ1 and SIZ0) and data size acknowledge pins (DSACK1 and DSACK0). Multiple bus cycles may be required for a transfer to or from an 8-bit port. For More Information On This Product to: www.freescale.com MC68331TS/D ...
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... Table 8 Size Signal Encoding SIZ0 Transfer Size 1 Byte 0 Word 1 Three Byte 0 Long Word FC1 FC0 Address Space 0 0 Reserved 0 1 User Data Space 1 0 User Program Space 1 1 Reserved 0 0 Reserved 0 1 Supervisor Data Space 1 0 Supervisor Program Space 1 1 CPU Space Go to: www.freescale.com 25 ...
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... DSACK1 inputs, as shown in the following table. Table 10 Effect of DSACK Signals DSACK1 DSACK0 For More Information On This Product, 26 Result 1 Insert Wait States in Current Bus Cycle 0 Complete Cycle —Data Bus Port Size is 8 Bits 1 Complete Cycle —Data Bus Port Size is 16 Bits 0 Reserved Go to: www.freescale.com MC68331TS/D ...
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... SIZ1, SIZ0, and ADDR0 for that bus cycle. For More Information On This Product, MC68331TS/D Byte Order OP0 OP1 OP0 Figure 8 Operand Byte Order Go to: www.freescale.com OP2 OP3 OP1 OP2 OP0 OP1 OP0 27 ...
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... For More Information On This Product, 28 Table 11 Operand Alignment SIZ1 SIZ0 ADDR0 DSACK1 to: www.freescale.com DSACK0 DATA DATA [15:8] [7: OP0 (OP0 OP0 (OP0 (OP0) OP0 1 0 OP0 (OP1 OP0 (OP0 OP0 OP1 0 X (OP0) OP0 1 0 OP0 (OP1 OP0 (OP0 OP0 OP1 0 X (OP0) OP0 1 0 OP0 ...
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... DSACK ASSIGNMENT GENERATOR REGISTER Chip Select Discrete Outputs CSBOOT — CS0 — CS1 — CS2 — CS3 PC0 CS4 PC1 CS5 PC2 CS6 PC3 CS7 PC4 CS8 PC5 CS9 PC6 CS10 ECLK Go to: www.freescale.com PIN PIN DATA REGISTER CHIP SEL BLOCK 29 ...
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... CSBOOT — CSPA1[4] CSPA1[3] 0 DATA7 1 DATA 1 DATA [7:6] [7:5] Alternate Signal CS10 ADDR23 CS9 ADDR22 CS8 ADDR21 CS7 ADDR20 CS6 ADDR19 Go to: www.freescale.com $YFFA44 CSPA0[2] CSPA0[1] CSBOOT 1 DATA1 1 1 DATA0 Discrete Output PC2 PC1 PC0 — — — — $YFFA46 CSPA1[2] ...
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... ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR ADDR to: www.freescale.com CS8/ CS7/ CS6/ ADDR21 ADDR20 ADDR19 CS8 CS7 CS6 CS8 CS7 ADDR19 CS8 ADDR20 ADDR19 ADDR21 ADDR20 ADDR19 $YFFA48 ADDR ADDR BLKSZ $YFFA4C–$YFFA74 ADDR ADDR BLKSZ 12 11 ...
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... The following table lists upper/lower byte options. For More Information On This Product, 32 Block Size Address Lines Compared 2 K ADDR[23:11 ADDR[23:13 ADDR[23:14 ADDR[23:16] 128 K ADDR[23:17] 256 K ADDR[23:18] 512 K ADDR[23:19 ADDR[23:20 STRB DSACK STRB DSACK to: www.freescale.com $YFFA4A SPACE IPL AVEC $YFFA4E–$YFFA76 SPACE IPL AVEC MC68331TS/D ...
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... Wait States 0100 4 Wait States 0101 5 Wait States 0110 6 Wait States 0111 7 Wait States 1000 8 Wait States 1001 9 Wait States 1010 10 Wait States 1011 11 Wait States 1100 12 Wait States 1101 13 Wait States 1110 Fast Termination 1111 External DSACK Go to: www.freescale.com 33 ...
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... For More Information On This Product, 34 Address Space 00 CPU Space 01 User Space 10 Supervisor Space 11 Supervisor/User Space IPL Description 000 Any Level 001 IPL1 010 IPL2 011 IPL3 100 IPL4 101 IPL5 110 IPL6 111 IPL7 PC6 PC5 to: www.freescale.com $YFFA41 PC4 PC3 PC2 PC1 PC0 MC68331TS/D ...
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... PEPA7 PEPA6 PEPA5 PEPA4 PEPA3 PEPA2 PEPA1 PEPA0 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 DATA8 Table 16 Port E Pin Assignments Port E Signal Bus Control Signal PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 Go to: www.freescale.com $YFFA11, $YFFA13 PE4 PE3 PE2 PE1 PE0 U ...
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... PFPA7 PFPA6 PFPA5 PFPA4 PFPA3 PFPA2 PFPA1 PFPA0 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 DATA9 Table 17 Port F Pin Assignments Port F Signal Alternate Signal PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 Go to: www.freescale.com $YFFA19, $YFFA1B PF4 PF3 PF2 PF1 PF0 U ...
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... CS[7:6] CS[8:6] CS[9:6] CS[10:6] DSACK0, DSACK1, AVEC, DS, AS, SIZ[1:0] IRQ[7:1] MODCLK Test Mode Disabled VCO = System Clock Background Mode Disabled Background Mode Enabled Go to: www.freescale.com Alternate Function (Pin Pulled Low) CSBOOT 8-Bit BR BG BGACK FC0 FC1 FC2 ADDR19 ADDR[20:19] ADDR[21:19] ADDR[22:19] ...
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... This mini- DDSYN is applied at power-on, start-up time is affected by specific DDSYN ramp-up time also affects pin state during reset. DD ramps up to the minimum specified value, and SIM DD Go to: www.freescale.com Function DSI/IFETCH DSO/IPIPE BKPT/DSCLK Discrete Input Discrete Input Discrete Input ...
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... IRQ[6:1] are maskable. IRQ7 is nonmaskable. The IRQ7 input is transition-sensitive in order to prevent redundant servicing and stack overflow. A nonmaskable interrupt is generated each time IRQ7 is as- serted, and each time the priority mask changes from %111 to a lower number while IRQ7 is asserted. For More Information On This Product, MC68331TS/D Go to: www.freescale.com ramp time and DD 39 ...
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... The periodic interrupt timer (PIT) in the SIM can generate internal interrupt requests of specific priority at predetermined intervals. By hardware convention, PIT interrupts are serviced before external inter- rupt service requests of the same priority. Refer to 3.2.7 Periodic Interrupt Timer for more information. For More Information On This Product to: www.freescale.com MC68331TS/D ...
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... TSTMSRB — Master Shift Register B TSTSC — Test Module Shift Count TSTRC — Test Module Repetition Count CREG — Test Module Control Register DREG — Test Module Distributed Register For More Information On This Product, MC68331TS/D Go to: www.freescale.com $YFFA02 $YFFA08 $YFFA30 $YFFA32 $YFFA34 $YFFA36 ...
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... Freescale Semiconductor, Inc. For More Information On This Product to: www.freescale.com MC68331TS/D ...
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... The user programming model remains unchanged from previous M68000 Family microprocessors. Ap- plication software written to run at the nonprivileged user level migrates without modification to the CPU32 from any M68000 platform. The move from SR instruction, however, is privileged in the CPU32 not privileged in the M68000. For More Information On This Product, MC68331TS/D Go to: www.freescale.com 43 ...
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... For More Information On This Product (USP CCR 0 A7' (SSP (CCR VBR 2 0 SFC DFC Go to: www.freescale.com Data Registers Address Registers User Stack Pointer Program Counter Condition Code Register Supervisor Stack Pointer Status Register Vector Base Register Alternate Function Code Registers MC68331TS/D ...
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... Included in the register indirect addressing modes are the capabilities to post-increment, predecrement, and offset. The program counter relative mode also has index and offset capabilities. In addition to these addressing modes, many instructions implicitly specify the use of the status register, stack point- er, or program counter. For More Information On This Product, MC68331TS to: www.freescale.com ...
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... If Rn < lower bound or Rn > upper bound, then 8, 16, 32 CHK exception 0 Destination 8, 16, 32 (Destination Source), CCR shows results 8, 16, 32 (Destination Source), CCR shows results 16 16, 32 (Destination Data), CCR shows results Go to: www.freescale.com Operation X Destination 10 Destination Destination Destination Destination X Destination Destination Destination 0 X/C ...
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... CCR Destination 16 Source CCR Destination Source SR 16 USP USP Listed registers Destination 16, 32 Source Listed registers 16 to: www.freescale.com Operation Upper bound, CCR shows result 1 PC Destination Destination Destination Destination Destination Destination (SSP); (SSP); (SSP); PC (SP); destination PC (SP EBI; STOP 0 X/C 47 ...
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... SR none SP 4 SP; Restore stack according to format (SP) CCR none (SP) PC none 8 Destination10 Source10 8 If condition true, then destination bits are set else, destination bits are cleared Data SR; STOP Go to: www.freescale.com Operation d); Dn [23 : 16] (An d 2 [ Destination Destination Destination Destination Destination ...
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... SSP; format/vector offset none SSP 4 SSP; PC vector address PC none If cc true, then TRAP exception 16 set, then overflow TRAP exception none Source 0, to set condition codes 8, 16 SP; (SP) An to: www.freescale.com Operation Destination Destination Destination Destination X Destination MSW LSW Temp Dn Temp (SSP); (SSP); SR (SSP ...
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... Current program counter is stacked at the location of the current stack pointer. Instruction execution begins at user patch code. Asserts RESET for 512 clock cycles. The CPU is not reset by this command. Synonymous with the CPU RESET instruction. NOP performs no operation and can be used as a null command. Go to: www.freescale.com MC68331TS/D ...
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... SUPV bit in the QSMCR. For More Information On This Product, MC68331TS/D QSPI INTERFACE LOGIC SCI Figure 12 QSM Block Diagram Go to: www.freescale.com MISO/PQS0 MOSI/PQS1 SCK/PQS2 PCS0/SS/PQS3 PCS1/PQS4 PCS2/PQS5 PCS3/PQS6 TXD/PQS7 ...
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... Input: Selects the QSPI PCS[3:1] Master Output: Selects Peripherals Slave None TXD Transmit Serial Data Output from SCI RXD Receive Serial Data Input to SCI Go to: www.freescale.com 0 QSM INTERRUPT VECTOR (QIVR) PQS DATA (PORTQS) PQS DATA DIRECTION (DDRQS) SPI STATUS (SPSR) Pin Function MC68331TS/D ...
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... The IARB field is used to arbitrate between simultaneous interrupt requests of the same priority. Each module that can generate interrupt requests must be assigned a unique, non-zero IARB field value. Re- fer to 3.8 Interrupts for more information. For More Information On This Product, MC68331TS SUPV to: www.freescale.com $YFFC00 IARB ...
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... DDRQS is configured. DDRQS must then be written to determine the direction of data flow and to output the value contained in register PORTQS. Subsequent data for output is written to PORTQS. For More Information On This Product ILSCI to: www.freescale.com $YFFC02 $YFFC04 0 QIVR $YFFC05 0 INTV MC68331TS/D ...
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... PQSPA1 PQSPA0 DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0 PQSPAR Bit Pin Function 0 PQS0 1 MISO 0 PQS1 1 MOSI 0 1 PQS2 1 SCK 0 PQS3 1 PCS0/SS 0 PQS4 1 PCS1 0 PQS5 1 PCS2 0 PQS6 1 PCS3 0 2 PQS7 1 TXD Go to: www.freescale.com $YFFC14 PQS4 PQS3 PQS2 PQS1 PQS0 $YFFC16 $YFFC17 ...
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... Assertion Causes Mode Fault 1 Chip-Select Output Slave 0 QSPI Slave Select Input 1 Disables Select Input Master DDQ[4:6 0 Disables Chip-Select Output ] 1 Chip-Select Output Slave 0 Inactive 1 Inactive Transmit DDQ7 X Serial Data Output from SCI Receive None NA Serial Data Input to SCI Go to: www.freescale.com Pin Function MC68331TS/D ...
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... For More Information On This Product, MC68331TS 80-BYTE QSPI RAM CHIP SELECT 4 COMMAND MSB LSB 8/16-BIT SHIFT REGISTER Rx/Tx DATA REGISTER 2 BAUD RATE GENERATOR Figure 13 QSPI Block Diagram Go to: www.freescale.com M S MOSI M S MISO PCS0/SS PCS[2:1] SCK QSPI BLOCK 57 ...
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... QSPI Control Register 0 SPCR1 QSPI Control Register 1 SPCR2 QSPI Control Register 2 SPCR3 QSPI Control Register 3 SPSR QSPI Status Register RAM QSPI Receive Data (16 Words) RAM QSPI Transmit Data (16 Words) RAM QSPI Command Control (8 Words CPOL CPHA to: www.freescale.com Function $YFFC18 0 SPBR MC68331TS/D ...
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... CPHA is used with CPOL to produce a desired clock/data relationship between master and slave devices. CPHA is set at reset. For More Information On This Product, MC68331TS/D BITS Bits per Transfer 0000 16 0001 Reserved 0010 Reserved 0011 Reserved 0100 Reserved 0101 Reserved 0110 Reserved 0111 Reserved 1000 8 1001 9 1010 10 1011 11 1100 12 1101 13 1110 14 1111 15 Go to: www.freescale.com 59 ...
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... Standard Delay after Transfer = [17/System Clock] Delay after transfer can be used to provide a peripheral deselect interval. A delay can also be inserted between consecutive transfers to allow serial A/D converters to complete conversion. For More Information On This Product, 60 SCK Baud Rate = System Clock/(2SPBR to: www.freescale.com $YFFC1A 0 DTL MC68331TS/D ...
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... HMIE — HALTA and MODF Interrupt Enable 0 = HALTA and MODF interrupts disabled 1 = HALTA and MODF interrupts enabled HMIE controls CPU interrupts caused by the HALTA status flag or the MODF status flag in SPSR. For More Information On This Product, MC68331TS ENDQP HMIE HALT to: www.freescale.com $YFFC1C NEWQP $YFFC1E 0 SPSR 61 ...
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... Receive data is information received from a serial device external to the MCU. Transmit data is infor- mation stored by the CPU for transmission to an external peripheral. Command control data is used to perform the transfer. Refer to the following illustration of the organization of the RAM. For More Information On This Product SPIF MODF HALTA RESET to: www.freescale.com $YFFC1F CPTQP MC68331TS/D ...
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... TRANSMIT COMMAND RAM TRD TRE TRF 53E 54F WORD Figure 14 QSPI RAM DSCK PCS3 PCS2 — — — DSCK PCS3 PCS2 Go to: www.freescale.com CR0 CR1 CR2 RAM CRD CRE CRF BYTE $YFFD00 $YFFD20 $YFFD40 1 0 PCS1 PCS0* — — PCS1 PCS0* 63 ...
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... SPE in SPCR1. 5.5 SCI Submodule The SCI submodule is used to communicate with external devices through an asynchronous serial bus. The SCI is fully compatible with the SCI systems found on other Motorola MCUs, such as the M68HC11 and M68HC05 Families. For More Information On This Product to: www.freescale.com MC68331TS/D ...
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... The following table lists the SCBR settings for standard and maximum baud rates using 16.78-MHz and 20.97-MHz system clocks. For More Information On This Product, MC68331TS/D Mnemonics Mode RXD Receiver Disabled Not Used Receiver Enabled Serial Data Input to SCI TXD Transmitter Disabled General-Purpose I/O Transmitter Enabled Serial Data Output from SCI SCBR to: www.freescale.com Function $YFFC08 ...
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... SCBR to: www.freescale.com Actual Rate with SCBR Value 20.97-MHz Clock — — 110.0 $1745 300.1 $0888 600.1 $0444 1200.3 $0222 2400.6 $0111 4783.6 $0089 9637.6 $0044 19275.3 $0022 38550.6 $0011 72817.8 $0009 655360 ...
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... The transmitter retains control of the TXD pin until completion of any character transfer in progress when TE is cleared. RE — Receiver Enable 0 = SCI receiver disabled (status bits inhibited SCI receiver enabled For More Information On This Product, MC68331TS/D PE Result 0 8 Data Bits 1 7 Data Bits, 1 Parity Bit 0 9 Data Bits 1 8 Data Bits, 1 Parity Bit Go to: www.freescale.com 67 ...
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... RDRF is set when the content of the receive serial shifter is transferred to the RDR. If one or more errors are detected in the received word, flag(s) NF, FE, and/or PF are set within the same clock cycle. For More Information On This Product TDRE TC RDRF RAF to: www.freescale.com $YFFC0C IDLE ...
Page 69
... SCDR is read, or the first eight data bits to be transmitted when SCDR is written. R8/T8 are used when the SCI is configured for 9-bit operation. When it is configured for 8-bit operation, they have no meaning or effect. For More Information On This Product, MC68331TS R8/T8 R7/T7 R6/T6 R5/ to: www.freescale.com $YFFC0E R4/T4 R3/T3 R2/T2 R1/T1 R0/ ...
Page 70
... SUPV bit in the GPTMCR. For More Information On This Product, 70 OC1/PGP3 OC2/OC1/PGP4 OC3/OC1/PGP5 OC4/OC1/PGP6 IC4/OC5/OC1/PGP7 PAI PCLK PRESCALER PWMA PWM UNIT PWMB BUS INTERFACE IMB Figure 15 GPT Block Diagram Go to: www.freescale.com GPT BLOCK MC68331TS/D ...
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... TIMER CONTROL 2 (TCTL2) TIMER MASK 1 (TMSK1) TIMER FLAG 1 (TFLG1) PWM CONTROL A (PWMA) PWM COUNT (PWMCNT) PWMB BUFFER (PWMBUFB) GPT PRESCALER (PRESCL) NOT USED Go to: www.freescale.com 0 PGP DATA (PORTGP) OC1 ACTION DATA (OC1D) PA COUNTER (PACNT) TIMER MASK 2 (TMSK2) TIMER FLAG 2 (TFLG2) PWM CONTROL C (PWMC) ...
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... FOC3 OC4I OC4F FOC4 I4/O5I OC5 I4/O5F FOC5 IC4 CFORC TFLG1 TMSK1 FORCE OUTPUT STATUS INTERRUPT COMPARE FLAGS ENABLES Figure 16 GPT Timer Block Diagram Go to: www.freescale.com 9 INTERRUPT REQUESTS PIN FUNCTIONS 1 PGP0 BIT 0 IC1 2 PGP1 BIT 1 IC2 3 PGP2 BIT 2 IC3 4 PGP3 BIT 3 ...
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... For More Information On This Product, MC68331TS/D 512 TO PULSE ACCUMULATOR EXT. TO PULSE ACCUMULATOR TO PULSE ACCUMULATOR CPR2 CPR1 CPR0 256 128 64 TO CAPTURE/ COMPARE 32 16 SELECT 8 4 EXT. 128 64 32 PWM UNIT SELECT EXT. PPR2 PPR1 PPR0 Go to: www.freescale.com TIMER TO GPT PRE BLOCK 73 ...
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... PCLK. For More Information On This Product, 74 16-BIT DATA BUS PWMA REGISTER PWMB REGISTER PWMABUF REGISTER PWMBBUF REGISTER "A" COMPARATOR "B" COMPARATOR "A" MULTIPLEXER "B" MULTIPLEXER Go to: www.freescale.com R PWMB LATCH PIN S F1B ZERO DETECTOR BIT SFB BIT 16/32 PWM BLOCK BLOCK ...
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... Specifies the priority level of interrupts generated by the GPT. IVBA — Interrupt Vector Base Address Most significant nibble of interrupt vector number generated by the GPT when an interrupt service re- quest is acknowledged. For More Information On This Product, MC68331TS SUPV IPL IVBA to: www.freescale.com $YFF900 IARB $YFF902 $YFF904 ...
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... PAIS — PAI Pin State (Read Only) PAEN — Pulse Accumulator System Enable 0 = Pulse accumulator disabled 1 = Pulse accumulator enabled For More Information On This Product PGP7 PGP6 PGP5 OC1D I4/O5 PACLK to: www.freescale.com $YFF906 PGP4 PGP3 PGP2 PGP1 PGP0 $YFF908 $YFF90A $YFF90C 0 PACNT MC68331TS/D ...
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... One on PAI inhibits counting Pulse Accumulator Clock Selected System Clock Divided by 512 Same Clock Used to Increment TCNT TOF Flag from TCNT External Clock, PCLK $YFF914, $YFF916, $YFF918, $YFF91A OL3 OM2 OL2 EDGE4 EDGE3 to: www.freescale.com $YFF90E, $YFF910, $YFF912 $YFF91C $YFF91E EDGE2 EDGE1 ...
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... Timer Disconnected from Output Logic Toggle OCx Output Line Clear OCx Output Line to 0 Set OCx Output Line to 1 Configuration Capture Disabled Capture on Rising Edge Only Capture on Falling Edge Only Capture on Any (Rising or Falling) Edge ICI TOI 0 PAOVI to: www.freescale.com $YFF920 PAII CPROUT CPR MC68331TS/D ...
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... Setting a bit in CFORC causes a specific output PWM pins. PWMC sets PWM operating con- ditions. For More Information On This Product, MC68331TS/D CPR[2:0] System Clock Divide-By Factor 000 4 001 8 010 16 011 32 100 64 101 128 110 256 111 PCLK ICF TOF 0 PAOVF FPWMA FPWMB PPROUT PPR to: www.freescale.com $YFF922 PAIF $YFF924 SFA SFB F1A F1B ...
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... Hz 641 Hz PCLK PCLK/256 PCLK/256 Go to: www.freescale.com SFA 16.78 MHz 20.97 MHz 256 Hz 320 Hz 128 Hz 160 Hz 64.0 Hz 80.0 Hz 32.0 Hz 40.0 Hz 16.0 Hz 20 ...
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... These read-only registers contain values associated with the duty cycles of the corresponding PWM. Reset state is $0000. PRESCL — GPT Prescaler The 9-bit prescaler value can be read from bits [8:0] at this address. Bits [15:9] always read as zeros. Reset state is $0000. For More Information On This Product, MC68331TS/D Go to: www.freescale.com $YFF926, $YFF927 $YFF928 $YFF92A, $YFF92B $YFF92C 81 ...
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... Expanded and revised QSM section. Made all register diagrams and bit mnemon- ics consistent. Added information concerning SPI and SCI operation. Page 77-89 Expanded and revised GPT section. Made all registerdiagrams and bit mnemonics consistent. Added information concerning input capture, output compare, and PWM operation. For More Information On This Product to: www.freescale.com MC68331TS/D ...
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... Freescale Semiconductor, Inc. For More Information On This Product, MC68331TS/D Go to: www.freescale.com 83 ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...