MC68331CEH16 Freescale, MC68331CEH16 Datasheet - Page 19

• Manufacturer Part Number: MC68331CEH16
• Manufacturer: Freescale

Specifications of MC68331CEH16

• Cpu Family: 68K/M683xx
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 16MHz
• Interface Type: QSPI/SCI/UART
• Total Internal Ram Size: 80Byte
• # I/os (max): 18
• Number Of Timers - General Purpose: 1
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: PQFP
• Program Memory Type: ROMLess
• Lead Free Status / RoHS Status: Compliant

SWP —Software Watchdog Prescale
SWT[1:0] —Software Watchdog Timing
HME —Halt Monitor Enable
BME —Bus Monitor External Enable
BMT[1:0] —Bus Monitor Timing
3.2.3 Bus Monitor
3.2.4 Halt Monitor
MC68331TS/D
This bit controls the value of the software watchdog prescaler.
This field selects the divide ratio used to establish software watchdog time-out period. The following ta-
ble gives the ratio for each combination of SWP and SWT bits.
This field selects a bus monitor time-out period as shown in the following table.
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
0 = Software watchdog clock not prescaled
1 = Software watchdog clock prescaled by 512
0 = Disable halt monitor function
1 = Enable halt monitor function
0 = Disable bus monitor function for an internal to external bus cycle.
1 = Enable bus monitor function for an internal to external bus cycle.
Freescale Semiconductor, Inc.
For More Information On This Product,
BMT
00
01
10
11
SWP
0
0
0
0
1
1
1
1
Go to: www.freescale.com
Bus Monitor Time-out Period
SWT
64 System Clocks
32 System Clocks
16 System Clocks
00
01
10
11
00
01
10
11
8 System Clocks
Ratio
2
2
2
2
2
2
2
2
11
13
15
18
20
22
24
9
19