MC9S08QG8CPBE Freescale, MC9S08QG8CPBE Datasheet - Page 135
MC9S08QG8CPBE
Manufacturer Part Number
MC9S08QG8CPBE
Description
Manufacturer
Freescale
Datasheet
1.MC9S08QG8CPBE.pdf
(314 pages)
Specifications of MC9S08QG8CPBE
Cpu Family
HCS08
Device Core Size
8b
Frequency (max)
20MHz
Interface Type
I2C/SCI/SPI
Total Internal Ram Size
512Byte
# I/os (max)
12
Number Of Timers - General Purpose
1
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
On-chip Adc
8-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Through Hole
Pin Count
16
Package Type
PDIP
Program Memory Type
Flash
Program Memory Size
8KB
Lead Free Status / RoHS Status
Compliant
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result of the conversion is transferred to ADCRH and ADCRL upon completion of the conversion
algorithm.
If the bus frequency is less than the f
cannot be guaranteed when short sample is enabled (ADLSMP=0). If the bus frequency is less than 1/11th
of the f
sample is enabled (ADLSMP=1).
The maximum total conversion time for different conditions is summarized in
The maximum total conversion time is determined by the clock source chosen and the divide ratio selected.
The clock source is selectable by the ADICLK bits, and the divide ratio is specified by the ADIV bits. For
example, in 10-bit mode, with the bus clock selected as the input clock source, the input clock divide-by-1
ratio selected, and a bus frequency of 8 MHz, then the conversion time for a single conversion is:
Freescale Semiconductor
ADCK
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Single or first continuous 10-bit
Subsequent continuous 10-bit;
Subsequent continuous 10-bit;
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Single or first continuous 8-bit
Subsequent continuous 8-bit;
Subsequent continuous 8-bit;
frequency, precise sample time for continuous conversions cannot be guaranteed when long
Conversion Type
Conversion time =
f
f
The ADCK frequency must be between f
maximum to meet ADC specifications.
BUS
BUS
f
f
BUS
BUS
> f
> f
> f
> f
ADCK
ADCK
ADCK
ADCK
Number of bus cycles = 3.5 μs x 8 MHz = 28 cycles
Table 9-12. Total Conversion Time vs. Control Conditions
/11
/11
MC9S08QG8 and MC9S08QG4 Data Sheet, Rev. 5
ADCK
23 ADCK cyc
8 MHz/1
frequency, precise sample time for continuous conversions
ADICLK
0x, 10
0x, 10
0x, 10
0x, 10
11
11
11
11
xx
xx
xx
xx
NOTE
ADLSMP
+
ADCK
0
0
1
1
0
0
1
1
0
0
1
1
5 bus cyc
minimum and f
8 MHz
20 ADCK cycles + 5 bus clock cycles
23 ADCK cycles + 5 bus clock cycles
40 ADCK cycles + 5 bus clock cycles
43 ADCK cycles + 5 bus clock cycles
5 μs + 20 ADCK + 5 bus clock cycles
5 μs + 23 ADCK + 5 bus clock cycles
5 μs + 40 ADCK + 5 bus clock cycles
5 μs + 43 ADCK + 5 bus clock cycles
Analog-to-Digital Converter (S08ADC10V1)
Max Total Conversion Time
= 3.5 μs
17 ADCK cycles
20 ADCK cycles
37 ADCK cycles
40 ADCK cycles
ADCK
Table
9-12.
133
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